Why does my Deinterlacer II license fail?
Description Due to a problem in the Quartus® Prime Standard edition software version 16.1, designs containing the Deinterlacer II IP only generate a time-limited programming file. Resolution To resolve this problem in the Quartus Prime Standard edition software version 16.1, download and install the patch from the links below: Download the Quartus Prime version 16.1 Patch 0.04 for Linux (.run) Download the Quartus Prime version 16.1 Patch 0.04 for Windows (.exe) Download the Quartus Prime version 16.1 Patch 0.04 Readme (.txt) This problem is scheduled to be fixed in a future release.How do I address known software issues for Stratix V, Arria V and Cyclone V devices in the Quartus II software version 13.0 SP1?
Description There is a single patch available to address known software issues for Stratix® V, Arria® V, and Cyclone® V devices in the Quartus® II software version 13.0 SP1. This patch will be updated periodically with the latest software fixes. Check here periodically for updated files. Refer to the readme file for each device patch for the date the file was updated and information on the issues fixed in that patch. Resolution Download and install the Stratix V/Arria V/Cyclone V device patch 1.dp6 from the appropriate link below. You must install the Quartus II software version 13.0 SP1 before installing this patch. Note that you should not install any non-Stratix V/Arria V/Cyclone V patches on the Quartus II software version 13.0 SP1 after installing this patch. Patch 1.dp6 includes all fixes from the previously-released patch. You can install 1.dp6 over the previous device patch, but you do not need to install the previous device patch before installing patch 1.dp6. Download the version 13.0 SP1 (Subscription Edition) patch 1.dp6 for Windows (.exe) Download the version 13.0 SP1 (Subscription Edition) patch 1.dp6 for Linux (.tar) Download the Readme for the Quartus II software version 13.0 SP1 (Subscription Edition) patch 1.dp6 (.txt) To install a previously-released version of the Quartus II software version 13.0 SP1 Stratix V/Arria V/Cyclone V device patch, select the appropriate link below. Device patch 1.dp5 Download the version 13.0 SP1 (Subscription Edition) patch 1.dp5 for Windows (.exe) Download the version 13.0 SP1 (Subscription Edition) patch 1.dp5 for Linux (.tar) Download the Readme for the Quartus II software version 13.0 SP1 (Subscription Edition) patch 1.dp5 (.txt) Device patch 1.dp1 Download the version 13.0 SP1 (Subscription Edition) patch 1.dp1 for Windows (.exe) Download the version 13.0 SP1 (Subscription Edition) patch 1.dp1 for Linux (.run) Download the Readme for the Quartus II software version 13.0 SP1 (Subscription Edition) patch 1.dp1 (.txt) Related Articles Are there any updates to the 10GBASE-KR PHY IP core in Quartus II software version 13.0 SP1 dp1? Errata - Stratix V and Arria V timing model issues in the Quartus II software version 13.0 SP1 Why is my HPS DDR3 controller failing calibration? Why is the Cyclone V SoC Device SDRAM interface Vref pin voltage incorrect ? Why do I see random read errors using DDR2 SDRAM Controller with UniPHY/ DDR3 SDRAM Controller with UniPHY or LPDDR2 SDRAM Controller with UniPHY? Why do I see timing problems reported when using derive_pll_clocks using UniPHY-based memory controllers?Why do I see random read errors when using the DDR2, DDR3/DDR3L and LPDDR2 UniPHY IP on the Arria V GX/GT/SX/ST and Cyclone V E/GX/GT/SE/SX/ST devices?
Description On rare occasions, a problematic code word transition and DQSEN assertion which occur close to the rising edge of DQSIN may create a race condition causing distortion and/or glitch at the DQS delay chain output resulting in random read errors. Check the table below for the use cases affected based on the Quartus® II software version used.: Device Memory Controller Location Memory Interface Type Frequency (MHz) Quartus II Prior to v13.0sp1.dp5 Quartus II v13.0sp1.dp5 to v14.0.2 Quartus II v14.1 or later Cyclone® V & Cyclone V SoC HPS DDR2 & DDR3 f <= 400 Sensitive to DQS Glitch Not Affected Not Affected LPDDR2 f <= 333 Not Affected FPGA LPDDR2 f <= 333 Not Affected DDR2 & DDR3 f < 250 Not Affected 250 <= f < =400 Sensitive to DQS Glitch Arria® V & Arria V SoC HPS DDR2 & DDR3 f < 450 Sensitive to DQS Glitch Not Affected Not Affected f >= 450 Sensitive to DQS Glitch LPDDR2 f <= 400 Not Affected FPGA LPDDR2 f <= 333 Not Affected DDR2 & DDR3 f < 250 Not Affected f >= 250 Sensitive to DQS Glitch Resolution This issue was partially corrected in Quartus II software release version 13.0sp1 and fully resolved in version 14.1 and later, through bypassing the DQS delay chain. Regenerate the EMIF IP and recompile the design with Quartus II version 14.1 or later. For designs using Cyclone V and Cylcone V SOC, and customers who are unable to upgrade to Quartus II version 14.1, please contact Altera using mySupport. For designs using Arria V devices, refer to the following link: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd06222015_999.html Patches for related Quartus II software versions can be obtained from the following links: Quartus II 13.0SP1: Download the version 13.0 Service Pack 1 patch 1.dp6c for Windows (.exe) Download the version 13.0 Service Pack 1 patch 1.dp6c for Linux (.run) Download the Readme for the Quartus II software version 13.0 Service Pack 1 patch 1.dp6c (.txt) Quartus II 13.1.4: Download the version 13.1 Update 4 patch 4.64 for Windows (.exe) Download the version 13.1 Update 4 patch 4.64 for Linux (.run) Download the Readme for the Quartus II software version 13.1 Update 4 patch 4.64 (.txt) Quartus II 14.0.2: Download the version 14.0 Update 2 patch 2.18 for Windows (.exe) Download the version 14.0 Update 2 patch 2.18 for Linux (.run) Download the Readme for the Quartus II software version 14.0 Update 2 patch 2.18 (.txt)Why does the Frame Buffer II (4K Ready) Intel® FPGA IP drop my ancillary (user) packets?
Description Due to a problem with the Frame Buffer II (4K Ready) Intel® FPGA IP when Module is Frame Writer only is selected, you cannot change the Maximum ancillary packets field. That field, under the Memory section of the parameter editor, will be greyed out and not editable. Frame buffer in frame writer mode, default Ancillary packets = 0 This field defaults to 0 (zero), which will cause all ancillary packets (also known as User packets) to be dropped. Resolution To work around this problem, de-select Module is Frame Writer only, change the Maximum ancillary packets per frame to your desired setting, then re-select Module is Frame Writer only. Frame buffer with frame writer mode off and Ancillary packets entered Frame buffer in frame writer mode, note Ancillary packets = 3 This problem is fixed in the Intel® Quartus® Prime Software version 18.0.Internal Error: Sub-system: PVAFAM_VISITOR, File: /quartus/power/pvafam/pvafam_titan_atom_visitor_main.cpp, Line: 2002 Atom type not supported by PVA
Description Due to a problem in the Quartus® II software version 14.0 and earlier, when you use the Altera Advanced SEU Detection IP, Error Message Register (EMR) unloader IP, and/or Fault Injection Debugger IP in your design, you may see this error during the PowerPlay Power Analyzer (PPPA) or using Generate PowerPlay Early Power Estimator File. Resolution To work around this problem, download and install patch 0.109 from the links below. You must install Quartus® II software version 13.1 before installing this patch. Download the version 13.1 patch 0.109 for Windows (.exe) Download the version 13.1 patch 0.109 for Linux (.run) Download the Readme for the Quartus II software version 13.1 patch 0.109 (.txt) This problem is fixed beginning with the Quartus® II software version 14.1.Why do the BSEL/CSEL pull-up and pull-down resistor values in Cyclone® V Device Schematic Review Worksheet not match with the Cyclone® V Device Family Pin Connection Guidelines?
Description In the Cyclone® V Schematic Review Worksheet version 4.0, it states that the pull-up and pull-down resistor values for BSEL/CSEL should be 4.7-kΩ and 10-kΩ which contradicts the information in the Cyclone® V Device Family Pin Connection Guidelines version 2.6 which recommends connecting a pull-up such as 10-kΩ or pull-down resistor such as 1-kΩ to select the desired boot select values. Please follow the Pin Connection Guidelines recommendation. Resolution The Cyclone® V Schematic review worksheet will be updated in future release to recommend resistor values of 1-kΩ pull down and 10-kΩ pull up for the BSEL/CSEL pins.Why is the input register not registered in the negative input pins, rx_in[*](n) of the ALTLVDS_RX megafunction?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 23.1 and earlier, you might see that the input register is not registered in the ALTLVDS_RX megafunction's negative input pins, rx_in[*](n). This is because the synthesis attributes "LVDS_RX_REGISTER=LOW" and "LVDS_RX_REGISTER=HIGH" are not assigned to the register in the Low-voltage differential signaling (LVDS) receiver interfaces. Resolution To work around the problem, add the following assignments in the Quartus® Settings File (.qsf): set_instance_assignment -name LVDS_RX_REGISTER LOW -to "altlvds_rx:ALTLVDS_RX_component|altlvdsrx_lvds_rx:auto_generated|altlvdsrx_lvds_ddio_in:ddio_in|ddio_l_reg" set_instance_assignment -name LVDS_RX_REGISTER HIGH -to "altlvds_rx:ALTLVDS_RX_component|altlvdsrx_lvds_rx:auto_generated|altlvdsrx_lvds_ddio_in:ddio_in|ddio_h_reg" This problem is currently scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.How do I configure and implement the Altera_PLL Cascading feature?
Description Compared to the conventional PLL Cascading; the Altera_PLL Cascading feature uses a dedicated cascading clock path between a pair of fPLLs to achieve better jitter performance and save global clock resources. Download this How-To document to learn Altera_PLL cascading configuration using megafunction and implementation.How do I calculate the frequency, phase shift and duty cycle for clocking ALTLVDS soft SERDES using external PLL mode?
Description Altera® devices have two types of implementation for SERDES blocks - hard SERDES and soft SERDES (built from logic cells). This document will discuss how to calculate the frequency, phase shift, and duty cycle for each of the clocks needed for the external PLL interface with soft SERDES. By selecting external PLL mode, you must set the PLL parameters, but you can access other features of the PLL such as clock switchover, PLL reconfiguration, and other output clocks which would otherwise not be available when using the internal PLL. Download this How-To document to learn how you can calculate the frequency, phase shift, and duty cycle for each of the clocks used for external PLL mode with soft SERDES. Related Articles Why does TimeQuest not analyze the tx_enable and tx_inclock or rx_enable and rx_inclock timing paths when using the ALTLVDS megafunction in external PLL mode?Embedded Peripherals IP User Guide - Altera® FPGA MII to RMII Converter Core - Table 461. The Parameter Scenario is incorrect
Description Table 461. Parameter Usage Scenario, in section 50. Intel® FPGA MII to RMII Converter Core in the Embedded Peripherals IP User Guide is incorrect: UG-01085 ID: 683130 Version 2021.12.13 50.3 Parameters Resolution The last two rows of this table should show MAC_SPEED as 0. MIIMAC2CORESPEED10 equals port ena_10 The correct table should look like the image shown below: This updated information has been added to Version 22.3 (2023.02.09) of the Embedded IP User Guide.