Why does my Quartus® Prime Installation fail with certificate error: SSL certificate problem: unable to get local issuer certificate (curlcode 60)?
Description Due to a problem in the Quartus® Prime Installer Software, you might see the error message shown below when you click Download & Install. This happens because the certificate bundled with the Quartus® Prime Installer Software is no longer accepted by the Altera® Content Delivery Network (CDN). As a result, secure downloads initiated during the installation process cannot be verified using the outdated certificate. The issue impacts the Installer for the following versions of Quartus software: Operating System Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) Microsoft Windows* 23.3 to 25.3.1 23.1std to 25.1std Linux* 23.3 to 23.4 23.1std The KDB workaround provided below applies to the following versions of Quartus software: Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) KDB workaround applies to 24.3 to 25.3.1 24.1std to 25.1std Note that for all other affected versions not covered by the KDB, you cannot use the installer workaround and must download Quartus software package files individually without using the installer. Separate packages can be found in the Individual Files tab of the Quartus Software Download pages. Resolution To work around this problem, follow these steps: 1. Download and unzip the cacert.zip, which contains the cacert.pem certificate file. 2. Specify the new certificate using one of the following methods: i) Command Line Interface (CLI): Open a command prompt or terminal and run the installer with the--cacert option, pointing to the new certificate file. Windows*: qinst_<version>.exe -sp"--cacert <full path to cacert.pem>" Linux*: qinst_<version>.run -- --cacert <full path to cacert.pem> ii) Graphical User Interface (GUI): - Open the Quartus® Prime Installer, navigate to Settings, locate the CA Certificate Path, and specify the full path to the cacert.pem certificate file. - Then, click Apply > OK. This problem is scheduled to be resolved in a future release of the Quartus® Prime Installer Software.Why does the text overlap in the ALTPLL IP Parameter Editor?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1, you might see that the text overlaps in the ALTPLL IP Parameter Editor on the Windows* Operating System. This prevents the ALTPLL IP from being instantiated. This problem does not occur in the Quartus® Prime Standard Edition Software version 24.1 and earlier. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 25.1, download and install the patch below: This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.
Error: TBBmalloc: skip allocation functions replacement in ucrtbase.dll: unknown prologue for function _msize
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1 or earlier, you may see this error message when generating Altera® IP on the Windows* 11 OS (Operating System). Resolution To work around this problem, follow these steps: Go to This PC, right-click, and select Properties. Click Advanced System Setting. In the Advanced tab, select Environment Variable. Under System variables, create a new variable with the name TBB_MALLOC_DISABLE_REPLACEMENT and value as 1. Click OK and restart the Quartus® Prime Software.Can I use the INPUT_TERMINATION .qsf assignment to assign an on-chip termination (OCT) to Transceiver REFCLK or Transceiver IO pins, in Stratix V, Arria V and Cyclone V devices?
Description No you cannot use the INPUT_TERMINATION assignment to assign an on-chip termination (OCT) to transceiver pins on Stratix® V, Arria® V and Cyclone® V devices. Instead, you must use one of the following qsf assignments : XCVR_GT_IO_PIN_TERMINATION (Stratix V GT transceiver IO pins ony) XCVR_IO_PIN_TERMINATION (transceiver IO pins) XCVR_REFCLK_PIN_TERMINATION (REFCLK pins) Refer to the Altera Transceiver PHY IP Core User Guide (PDF) for more information on how to use these assignments. Note that if you use an INPUT_TERMINATION assignment on the transceiver pins, it will be ignored by the Quartus® II software and the default termination option will be assigned to these pins. Related Articles Error (169033): I/O pin with Termination logic option setting Differential cannot be placed inside I/O Bank because the I/O bank does not support the requested Termination setting.Error : FLEXlm version of vendor daemon is too old
Description In the Questa* FPGA Edition simulator and Questa* FPGA Starter Edition simulator version 2024.1, you might see this error or the following error if you are using the MGCLD daemon v11.16.4 “Unable to checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER, MGLS_LICENSE_FILE, LM_LICENSE_FILE) is set correctly” Resolution To avoid this error, upgrade to the Siemens* Flexlm (SALTD) daemon v11.19.5 Download the daemon from the download page There is a change to the Siemens* License in v11.19.5.0. If you’re running a floating license server for Siemens* licenses, manually change the VENDOR daemon line in the license file from mgcld to saltd, for example: VENDOR saltd <path to saltd> Note: Do not change any of the INCREMENT lines. Leave the INCREMENT lines with the original vendor daemon name (mgcld).Does the Advanced clock phase control adjustment in the HPS DDR3 work?
Description You may notice the Advanced clock phase control setting in the HPS GUI PHY Settings tab. Changing the phase value has no effect on the phase of the PLL output clocks. Resolution The Advanced clock phase control adjustment will be removed in a future version of the Quartus® II software. This problem was fixed in Quartus® II software version 13.1How do I instantiate a differential input or output buffer in my design?
Description You can instantiate a differential input or output buffer in your design using the ALTIOBUF Intel® FPGA IP core available in the Intel® Quartus® Prime Software. Resolution The ALTIOBUF Intel® FPGA IP core allows you to specify your input or output pin as a differential receiver or transmitter and then you need to port both the positive and negative signals to I/O pins. This Intel FPGA IP core is supported beginning with the Stratix® III and Cyclone® III device families. For Stratix® II, Cyclone® II, Arria® GX, and previous device families, you cannot instantiate a differential buffer in your design. Instead, use the positive leg of the differential pair in your design, and locate that pin in the Assignment Editor. Give that pin an I/O standard assignment with a value of "LVDS" or the differential I/O standard you wish to use. Refer to the device handbook for a complete listing of the supported I/O standards. The negative leg will automatically be assigned to the corresponding complimentary pin by the fitter when you compile your design. This method is supported for all device families that support differential I/O standards such as LVDS. For more information on the ALTIOBUF Intel FPGA IP core, refer to the ALTIOBUF IP Core User Guide (PDF). Related Articles Internal Error: Sub-system: FIOMGR, File: /quartus/fitter/fiomgr/fiomgr_io_power_region.cpp, Line: 2460cc1plus.exe: out of memory allocating 65536 bytes
Description This error may be seen when compiling large software projects on Windows platforms. cc1plus.exe is a 32bit Windows application and has access to 2GB of memory on Windows. Resolution To work around this problem, Windows can be configured to allow 32bit applications access to a 3GB address space. 1. Enable 3GB address space for 32bit applications on Windows: From Windows command prompt run: bcdedit /set IncreaseUserVa 3072 2. Allow cc1plus.exe to use the larger address space From Windows command prompt run: editbin /LARGEADDRESSAWARE "<path>/cc1plus.exe“ This problem is scheduled to be fixed in a future release of the SoC EDS Software.Cyclone® V Device Handbook: Known Issues
Description Issue 338064: Volume 1, Chapter 8 SEU Mitigation for Cyclone® V Devices, Version 2015.06.12 In page 8-9, Timing section states as follows: The CRC_ERROR pin is always driven low during CRC calculation for a minimum of 32 clock cycles. When an error occurs, the pin is driven high once the EMR is updated or 32 clock cycles have lapsed, whichever comes last. Therefore, you can start retrieving the contents of the EMR at the rising edge of the CRC_ERROR pin. The pin stays high until the current frame is read and then driven low again for a minimum of 32 clock cycles. But this is incorrect. It should state as follows: The CRC_ERROR pin is always driven low during CRC calculation. When an error occurs, the EDCRC hard block takes 32 clock cycles to update the EMR, the pin is driven high once the EMR is updated. Therefore, you can start retrieving the contents of the EMR at the rising edge of the CRC_ERROR pin. The pin stays high until the current frame is read and then driven low again for 32 clock cycles. Figure 8-6 states CRC Calculation (minimum 32 clock cycles), but it should state CRC Calculation (32 clock cycles). Issue 132933: Volume1 Chapter 8, SEU Mitigation for Cyclone V Devices, version 2014.06.30 Table 8-3 incorrectly shows Cyclone E in the variant column. It should show Cyclone V E. Issue 136679: I/O Features in Cyclone V Devices, Version 2013.06.21 Page 33 states the weak pull-up resistor is not supported on dedicated clock pins. This is incorrect, the weak pull-up resistor is supported on dedicated clock pins. Issue 138112: Cyclone V Device Datasheet, Version 1.3 2012.12.28 Table 5-24 shows the programmable IOE features and settings for Cyclone V devices. The pre-emphasis feature row indicates the assignments apply to allow values- 0 (enabled) and 1(disabled). This cell should be updated to 0(disable) and 1(enable). Issue 156380: Clock Networks and PLLs in Cyclone V Devices, Version 2013.05.06 There are two bullets for requirements when using automatic clock switchover, the first one is incorrect. It says: "Both clock inputs must be running." The purpose of automatic clock switchover is to switch between clocks if one stops running. The actual requirement is both clocks need to be running when the FPGA is configured. The bullet should say: "Both clock inputs must be running when the FPGA is configured." Issue 140192: I/O Features in Cyclone V Devices: Version 2013.6.21 Table 5-10 indicates the 3.3V input signal is not supported when VCCIO=2.5V in MuliVolt I/O Support. The table is incorrect and the 2.5V VCCIO can support a 3.3V input signal. Issue 138311: Cyclone V Device Datasheet: Version 3.4 Table 51 shows the value for t CO would be a maximum of 4us but this is incorrect, the maximum value for t CO should be 4ns. Issue 110591: Cyclone V Device Overview: Version 2012.12.28 Page 14, Figure 7 shows a M385 pin package is available, this is a typo and will be updated to a M386 pin package. Issue 98650: Volume 1, Chapter 4, Clock Networks and PLLs in Cyclone V Devices, Version 2012.12.28 The handbook currently states that External Feedback mode is supported on all Cyclone V PLLs, except on the corner fractional PLLs. This is incorrect. The handbook should state that External Feedback mode is supported on all Cyclone V PLLs, except on the strip fractional PLLs. Issue 92790: Volume 1, Chapter 5, I/O Features in Cyclone V Devices, Version 2012.12.28 Table 5-15: Modular I/O Banks for Cyclone V E A7 F672 package should have the following I/O counts: Bank 6A = 48 I/O pins available Bank 5B = 32 I/O pins available Issue 92829: Volume 1, Chapter 5, I/O Features in Cyclone V Devices, Version 2012.12.28 Table 5-23 should indicate that Current Strength 16, 8, 4 mA are available for 3.3V LVTTL I/O standards. Only 8, 4 mA is supported in HPS. Resolution Resolved Issues: Issue 67593: Volume 1, Chapter 5, I/O Features in Cyclone V Devices, Version 2.0 Statements implying VREF pins are available as user I/O pins removed in version 2012.12.28, VREF pins do not have user I/O pin functionality. Issue 41653: Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices, version 1.1 Configuration Schemes for Cyclone V Devices for AS (x1, x4) modes update to show AS configuration supports only 3.0 and 3.3V. Issue 41653: Device Interfaces and Integration Basics for Cyclone V Devices, version 1.1 This chapter has been integrated to the device handbook, volume 1. Active serial configuration has been updated to show support only for 3.0 and 3.3V VCCPGM, 1.8V is not supported. Issue 30381: Volume 2, Chapter 5, I/O Features in Cyclone V Devices, Version 1.1 Table 5-3 updated to show the 3.3-V LVCMOS I/O standard supports only a 2mA current strength.
