EMIF Maximum Frequency Specification Update
Description This problem affects DDR2 and DDR3 products. DDR2 and DDR3 interfaces on Arria V GX/GT/SoC or Cyclone V and SoC devices may experience problems achieving timing closure at certain maximum frequencies. Resolution The workaround for this issue is to apply the appropriate solution for your configuration, as described below. (The stated performances apply to component topologies only; DDR2 DIMM configurations are not affected, and DDR3 DIMM configurations are not supported.) DDR2 SDRAM EMIF Maximum Frequency Specification Update for Arria V GX/GT/SoC or Cyclone V and SoC Devices For Arria V GX, -C5 speed grade device interfacing with a DDR2 SDRAM component with 2 chip selects using hard memory controller at 350 MHz: Upgrade the 400 MHz DDR2 SDRAM component to a 533 MHz DDR2 SDRAM component to achieve an interface frequency of 333 MHz. For Arria V GX, -C5 speed grade device interfacing with a DDR2 SDRAM component with 1 chip select using hard memory controller at 400 MHz: Upgrade the 400 MHz DDR2 SDRAM component to a 533 MHz DDR2 SDRAM component to achieve the specified maximum frequency. * If you experience timing failure with this configuration in version 13.0 SP1 DP5, file a service request to Altera. This specification is supported in version 13.1. For Arria V GX/GT, -I5 speed grade device interfacing with a DDR2 SDRAM component with 1 chip select using hard memory controller at 400 MHz: Upgrade the 400 MHz DDR2 SDRAM component to a 533 MHz DDR2 SDRAM component to achieve the specified maximum frequency. * If you experience timing failure with this configuration in version 13.0 SP1 DP5, file a service request to Altera. This specification is supported in version 13.1. DDR3/DDR3L SDRAM EMIF Maximum Frequency Specification Update for Arria V GX/GT/SoC or Cyclone V and SoC Devices For Cyclone V SoC (SE/SX), -A7 speed grade device interfacing with a DDR3 or DDR3L SDRAM component, with 1 chip select using HPS hard memory controller at 400 MHz: Upgrade the 533 MHz DDR3 SDRAM component to a 667 MHz DDR3 SDRAM component to achieve the specified maximum frequency. * If you experience timing failure with this configuration in version 13.0 SP1 DP5, file a service request to Altera. This specification is supported in version 13.1. For Cyclone V GX/E, -C6 speed grade device interfacing with a DDR3 or DDR3L SDRAM component, with 2 chip selects using hard memory controller at 400 MHz: Upgrade the 533 MHz DDR3 SDRAM component to a 667 MHz DDR3 SDRAM component to achieve the specified maximum frequency. For Cyclone V SoC (SE/SX/ST), -I7 speed grade device interfacing with a DDR3 or DDR3L SDRAM component, with 1 chip select using HPS hard memory controller at 400 MHz: Upgrade the 533 MHz DDR3 SDRAM component to a 667 MHz DDR3 SDRAM component to achieve the specified maximum frequency. For Arria V GX/GT, -I3 speed grade device interfacing with a DDR3 or DDR3L SDRAM component, with 1 chip select using hard memory controller at 533 MHz: Upgrade the 533 MHz DDR3 SDRAM component to a 667 MHz DDR3 SDRAM component to achieve the specified maximum frequency. For Arria V GX, -C4 speed grade device interfacing with a DDR3 or DDR3L SDRAM component, with 1 chip select using hard memory controller at 533 MHz: Upgrade the 533 MHz DDR3 SDRAM component to a 667 MHz DDR3 SDRAM component to achieve the specified maximum frequency. For Arria V GX, C5 speed grade device interfacing with a DDR3 or DDR3L SDRAM component, with 1 chip select using either soft or hard memory controllers at 533 MHz: Upgrade the 533 MHz DDR3 SDRAM component to a 667 MHz DDR3 SDRAM component to achieve the specified maximum frequency and avoid running memory interface at 425-449 MHz. For Arria V GX/GT, I5 speed grade device interfacing with a DDR3 or DDR3L SDRAM component, with 1 chip select using either soft or hard memory controllers at 533 MHz: Upgrade the 533 MHz DDR3 SDRAM component to a 667 MHz DDR3 SDRAM component to achieve the specified maximum frequency and avoid running memory interface at 420-449 MHz. This issue will not be fixed. The solutions for maximum frequency specifications have been updated in the External Memory Interface Spec Estimator.Why is an unconstrained clock error reported when using the Error Message Register Unloader Intel® FPGA IP?
Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 20.1 and later, an unconstrained clock is reported in the check timing report in the Timing Analyzer as shown below when using the Error Message Register Unloader Intel® FPGA IP. This problem occurs on Cyclone® V FPGAs. emr_unloader_component|current_state.STATE_CLOCKHIGH ; Node was determined to feed a clock port but was found without an associated clock assignment. emr_unloader_component|crcblock_atom:emr_atom|generate_crcblock_atom.emr_atom~FF_** ; No clock feeds this register's clock port. Resolution To work around this problem, add the create_generated_clock constraint to your SDC file. For example: create_generated_clock -name emr_unloader_STATE_CLOCKHIGH -source [get_ports {<clock name>}] [get_keepers {<path to IP>|EMR_unloader0:inst|EMR_unloader0_emr_unloader2_0:emr_unloader2_0|altera_emr_unloader:emr_unloader_component|current_state.STATE_CLOCKHIGH}]Is there an issue with the output clock frequency if you set the duty cycle values other than 50% in the PLL Intel® FPGA IP?
Description Yes, you may encounter an issue with the output clock frequency when setting duty cycle values other than 50% in the PLL Intel FPGA IP. This can occur when using the Quartus® II software version 13.0sp1 and earlier. The problem occurs if the C-Counter Hi Divide and C-Counter Low Divide parameters are calculated incorrectly by the PLL Intel FPGA IP. The Compilation report => Fitter => Resource Section => PLL Usage Summary will show the actual output clock frequency. If the reported output clock frequency is not correct, then the C-Counter Hi Divide or C-Counter Low Divide parameter is not correct. Resolution The C counters are used to divide the voltage-controlled oscillator (VCO) frequency to the desired output frequency. The sum of the C-Counter Hi Divide and C-Counter Low Divide parameters is the resulting divider value of the VCO frequency. For example, if the VCO is running at 840 MHz, and the desired output clock is 105 MHz, then a total divide value of 8 is required. For a 50% duty cycle, the high and low counts should be divided evenly between the C-Counter Hi Divide and C-Counter Low Divide parameters, in which the divide value for each parameter is 4. To create other duty cycle values, you can adjust the C-Counter Hi Divide and C-Counter Low Divide parameters as required. You need to ensure the sum of these parameters is equal to the total divide value in order to generate the desired output clock frequency. If the total divide value is an odd value, then you need to turn on the C-Counter Odd Divide Enable parameter if a 50% duty cycle is required. For example, if the VCO is running at 840 MHz and the desired output clock frequency is 120 MHz, then a total divide value of 7 is required. In this case the C-Counter Hi Divide parameter would be 4, the C-Counter Low Divide parameter would be 3, and set the C-Counter Odd Divide Enable parameter to True. If a duty cycle other than 50% is required, you will need to adjust the C-Counter Hi Divide parameter and C-Counter Low Divide parameter as required. You need to ensure the sum of these parameters is equal to the total divide value in order to generate the desired output clock frequency. To fix this problem in your design, open the <PLL instance name>_0002.v file and locate the C-Counter Hi Divide and C-Counter Low Divide parameters for the affected output clock(s). Adjust these parameters as required to create the correct output clock frequency and desired duty cycle. Referring to the examples above, if the VCO is running at 840 MHz and the desired output clock frequency is 105 MHz with a 12.5% duty cycle, the following parameters will be required: C-Counter Hi Divide = 1 C-Counter Low Divide = 7 C-Counter Odd Divide Enable = False Due to the problem in the PLL Intel FPGA IP calculation, set the following parameters for a 120 MHz output clock frequency: C-Counter Hi Divide = 1 C-Counter Low Divide = 6 C-Counter Odd Divide Enable = True To fix the parameters in this example, the C-Counter Low Divide parameter should be set to 7, and the C-Counter Odd Divide Enable parameter should be set to False in the <PLL instance name>_0002.v file.Error: Error during execution of "{C:/altera/12.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Description You may experience the above error when generating a UniPHY-based memory controller. The error occurs because one of the system environment variables 'TEMP' points to a network drive and not a local drive. Resolution The workaround is to point the TEMP variable to the local machine, such as the C: drive. Also the variable HOMEDRIVE should point to the local machine.Why does my Avalon Memory Mapped bus hang when accessing the transceiver reconfiguration controller in Arria V, Cyclone V and Stratix V devices?
Description Avalon® Memory Mapped accesses to the transceiver reconfiguration controller in the Arria® V, Cyclone® V, and Stratix® V, devices will hang if the accesses are made to addresses outside of the specified address space of Table 16-8 of the Altera Transceiver Phy IP Core User Guide. http://www.altera.com/literature/ug/xcvr_user_guide.pdfU-Boot Times Out During FPGA Programming
Description On the Cyclone V SoC HPS, U-Boot might time out without completing, and report an error code of -6, indicating that the FPGA control block cannot obtain valid data. This can happen if the FPGA manager exits the initialization phase before U-Boot tests for it. As a result, the value of the FPGA manager’s stat.mode field is USERMODE , and U-Boot times out waiting for stat.mode to be set to INITPHASE . Resolution Edit the U-Boot source file arch/arm/cpu/armv7/socfpga/fpga_manager.c. Modify the stat.mode test to allow either stat.mode = INITPHASE or stat.mode = USERMODE . Alternatively, upgrade to v13.1 or later.Error (10232): Verilog HDL error at bitec_dp_rx_ss_audio.v(420): index 64 cannot fall outside the declared range [63:0] for vector "fifo_data_x2chan_mux"
Description Due to a problem in the Quartus® II software version 14.0, you may see this error when compiling a design that contains the DisplayPort IP that has more that 2 Audio receive channels enabled. Resolution To work around this problem in the Quartus® II software version 14.0, replace the existing file <IP variation name>/bitec_dp/rx/ss/bitec_dp_rx_ss_audio.v with the attached version of this file. bitec_dp_rx_ss_audio.v This problem has been fixed starting in the v14.1 release of the Quartus® II software.Internal Error: Sub-system: ASM, File: /quartus/comp/asm/asm_split_bits_utility.cpp, Line: 621 Bad mask!
Description Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error when compiling a Cyclone® IV or Cyclone V design using the Functional Safety Separation Flow. During partition import of strictly preserved safety partitions, routes to top-level safe IO buffers are not correctly preserved. When the Assembler detects the preservation mismatch during the Design Modification Flow it fails with this internal error. Resolution To work around this problem, for the Quartus II software version 13.1 Update 4, download and install patches 4.30 and 4.55 from the links below. You must install the Quartus II software version 13.1 Update 4 before installing these patches. Download the Quartus II software version 13.1 Update 4 patch 4.30 for Windows (.exe) Download the Quartus II software version 13.1 Update 4 patch 4.30 for Linux (.run) Download the Readme for the Quartus II software version 13.1 Update 4 patch 4.30 (.txt) Download the Quartus II software version 13.1 Update 4 patch 4.55 for Windows (.exe) Download the Quartus II software version 13.1 Update 4 patch 4.55 for Linux (.run) Download the Readme for the Quartus II software version 13.1 Update 4 patch 4.55 (.txt) For the Quartus II software version 14.1 Update 1, download and install patch 1.04 from the links below. You must install the Quartus II software version 14.1 Update 1 before installing this patch. Download the Quartus II software version 14.1 Update 1 patch 1.04 for Windows (.exe) Download the Quartus II software version 14.1 Update 1 patch 1.04 for Linux (.run) Download the Readme for the Quartus II software version 14.1 Update 1 patch 1.04 (.txt) This problem is fixed beginning with version 15.0 of the Quartus II software.How do I determine the phase shift and duty cycle for the required clocks if I am using ALTLVDS_RX and ALTLVDS_TX in external PLL mode?
Description You can determine the phase shift and duty cycle for the required clocks when using ALTLVDS_RX and ALTLVDS_TX in external PLL mode by first compiling an example design with ALTLVDS_RX or ALTLVDS_TX using an internal PLL. Use the settings that the Quartus® II software uses to configure the internal PLL in the example design as the settings you enter in the external PLL. To check the PLL settings in the Fitter report, expand the Resource section, and then expand PLL Usage. The report shows the duty cycle, phase shift and clock frequency for each of the required clocks for the ALTLVDS_RX and ALTLVDS_TX interfaces. You can then use these parameters for the external PLL settings in your design. Related Articles How do I implement ALTLVDS in External PLL Mode for Stratix V, Arria V, and Cyclone V devices? How do I implement the ALTLVDS_RX and ALTLVDS_TX megafunctions with External PLL mode in Arria II GX devices? How do you implement the altlvds megafunction with the External PLL option in Stratix III devices?How should the data in the RPD file be set up for programming quad-serial (EPCQ) devices that are 256Mb or larger?
Description When programming EPCQ devices that are 256Mb or larger with an RPD file in Active Serial (AS) mode, you need to set it in 4-byte addressing mode before programing, otherwise it will cause a configuration failure. Resolution To set the EPCQ device in 4-byte addressing mode, refer to 4BYTEADDREN operations in Quad-Serial Configuration (EPCQ) Devices Datasheet (PDF).