Error: TBBmalloc: skip allocation functions replacement in ucrtbase.dll: unknown prologue for function _msize
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1 or earlier, you may see this error message when generating Altera® IP on the Windows* 11 OS (Operating System). Resolution To work around this problem, follow these steps: Go to This PC, right-click, and select Properties. Click Advanced System Setting. In the Advanced tab, select Environment Variable. Under System variables, create a new variable with the name TBB_MALLOC_DISABLE_REPLACEMENT and value as 1. Click OK and restart the Quartus® Prime Software.
Why does the text overlap in the ALTPLL IP Parameter Editor?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1, you might see that the text overlaps in the ALTPLL IP Parameter Editor on the Windows* Operating System. This prevents the ALTPLL IP from being instantiated. This problem does not occur in the Quartus® Prime Standard Edition Software version 24.1 and earlier. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 25.1, download and install the patch below: This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.Why does Linux report "DMA engine initialization failed" error when EMAC uses GMII interface?
Description When supporting GMII interface for HPS EMAC, there are three clocks exported to FPGA: emac_tx_clk_i(input), emac_rx_clk_i(input), emac_gtx_clk(output) The Linux would report below error if the emac_tx_clk_i clock is not connected correctly: ...... [ 4.291414] socfpga-dwmac ff802000.ethernet: Failed to reset the dma [ 4.297785] socfpga-dwmac ff802000.ethernet eth1: stmmac_hw_setup: DMA engine initialization failed [ 4.306806] socfpga-dwmac ff802000.ethernet eth1: stmmac_open: Hw setup failed ...... Resolution Besides connecting the emac_rx_clk_i(125MHz) for GMII, the emac_tx_clk_i also needs to be connected correctly (2.5MHz or 25MHz), although it is not used in GMII mode. The emac_tx_clk_i requirement information has been added in the HPS document beginning with version 21.2.Error : FLEXlm version of vendor daemon is too old
Description In the Questa* FPGA Edition simulator and Questa* FPGA Starter Edition simulator version 2024.1, you might see this error or the following error if you are using the MGCLD daemon v11.16.4 “Unable to checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER, MGLS_LICENSE_FILE, LM_LICENSE_FILE) is set correctly” Resolution To avoid this error, upgrade to the Siemens* Flexlm (SALTD) daemon v11.19.5 Download the daemon from the download page There is a change to the Siemens* License in v11.19.5.0. If you’re running a floating license server for Siemens* licenses, manually change the VENDOR daemon line in the license file from mgcld to saltd, for example: VENDOR saltd <path to saltd> Note: Do not change any of the INCREMENT lines. Leave the INCREMENT lines with the original vendor daemon name (mgcld).How to mitigate the security vulnerability in the Nios® II Command Shell utility?
Description Due to a problem in the Quartus ® Prime Standard and Lite Edition Software version 19.1 through 24.1, the Nios® II Command Shell utility included in the Quartus ® Prime Software for Windows* is vulnerable to a Current Working Directory (CWD) planting attack. The Linux* versions are not affected. Resolution To work around this problem, replace the “Nios II Command Shell.bat” Windows Batch File located in the <drive>:\<edition>\<version number>\nios2eds\, with the attached file below. This problem is fixed beginning with the Quartus® Prime Standard and Lite Edition Software version 25.1.Why does Nios® V processor design fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus® Prime project instead of the QIP file?
Description In the Quartus ® Prime Standard Edition software version 25.1, any Nios ® V processor designs might fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus ® Prime project. Here are the possible error messages that you might receive: Error (10170): Verilog HDL syntax error at niosv_cpp_fsm.sv(1418) near text: "'"; expecting ":", or "?", or binary operator. Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (16950): Verilog HDL error at : decimal constant 00000000000000010000000000000000 is too large, using 1874919424 instead Error (16814): Verilog HDL error at ... : unknown literal value 00000000000000010000000000000000 for parameter ... ignored This is because the Quartus ® Prime Standard Edition software version 25.1 has been updated to adhere to the software requirements below. This requirement is not mandatory in prior versions of the Quartus ® Prime Standard Edition software. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, Remove the QSYS file from the project using the Remove Files in Project function. Add the QIP file to the project using the Add Files in Project function. Related Articles ERROR building simple NIOS® V Compact project Nios® V Synthesis Fails with Quartus® Prime 25.1 LiteWhy does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IPWhy is my Cyclone V or Stratix V Altera_PLL reset port is inverted in simulation?
Description Due to a problem in the Quartus® II software version 13.1, you see the the Altera PLL reset port is inverted in gate level simulation. This problem occurs in Cyclone® V or Stratix® V designs when advanced mode or reconfiguration is enabled in the Altera_PLL. Resolution To work around this problem in ModelSim, add the following switch to the vlog command define POSTFIT_SIM_USE_ICD_PLL_MODEL For example add the following lines to the *_run_msim_gate_verilog.do file For Cyclone V designs vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/mentor/cyclonev_*.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/cyclonev_atoms.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL For Stratix V designs vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/mentor/stratixv_*.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/stratixv_atoms.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/altera_primitives.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/altera_lnsim.sv vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/220model.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/sgate.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/altera_mf.v vsim -t 1ps transport_int_delays transport_path_delays -voptargs= acc gate_work.<top_level_design.vho/vo> Related Articles Why does the Altera PLL IP signal phase_done not assert in gate-level simulation of dynamic phase shift?Why does Ashling* RiscFree* IDE for Altera® FPGAs fail to debug a Nios® V processor C++ software project in Windows?
Description Due to a problem with the Ashling* RiscFree* IDE for Altera ® FPGAs software, debugging a Nios ® V processor software project may fail when it is written in the C++ language. This is because there is a bug in the processor toolchain from the Ashling* RiscFree* IDE for Altera ® FPGAs software. C projects are not affected by this issue. You might receive the following error messages. Error Messages How is RISC-V GDB executed? Error in services launch sequence: GDB prompt not read From Ashling* RiscFree* IDE for Altera software ../../../gdb/gdb/cp-name-parser.y:192: internal-error: fill_comp: Assertion ‘i’ failed. Executing riscv32-unknown-elf-gdb commands in the command-line interface The affected Ashling* RiscFree* IDE for Altera ® FPGAs software versions are: 24.3.1 (version dated 9 th Aug 2024) 24.4.0 (version dated 27 th Sep 2024) 25.1.1 (version dated 31 st Jan 2025) Note that: This problem only affects Windows environments. C projects are not affected by this problem. Resolution This problem is fixed beginning with the Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025). You can download Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025) separately from Quartus® Prime Pro Edition Installer for software version 25.1.1. Follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select Windows as the Operating System. Download the Quartus® Prime Pro Edition Installer for software version 25.1.1. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and Tools Note: Refrain from using the Quartus® Prime Pro Edition Installer for software version 25.3 to resolve this problem. The installer contains the older version of the Ashling* software (Software version 25.1.1).Cyclone® V Device Handbook: Known Issues
Description Issue 338064: Volume 1, Chapter 8 SEU Mitigation for Cyclone® V Devices, Version 2015.06.12 In page 8-9, Timing section states as follows: The CRC_ERROR pin is always driven low during CRC calculation for a minimum of 32 clock cycles. When an error occurs, the pin is driven high once the EMR is updated or 32 clock cycles have lapsed, whichever comes last. Therefore, you can start retrieving the contents of the EMR at the rising edge of the CRC_ERROR pin. The pin stays high until the current frame is read and then driven low again for a minimum of 32 clock cycles. But this is incorrect. It should state as follows: The CRC_ERROR pin is always driven low during CRC calculation. When an error occurs, the EDCRC hard block takes 32 clock cycles to update the EMR, the pin is driven high once the EMR is updated. Therefore, you can start retrieving the contents of the EMR at the rising edge of the CRC_ERROR pin. The pin stays high until the current frame is read and then driven low again for 32 clock cycles. Figure 8-6 states CRC Calculation (minimum 32 clock cycles), but it should state CRC Calculation (32 clock cycles). Issue 132933: Volume1 Chapter 8, SEU Mitigation for Cyclone V Devices, version 2014.06.30 Table 8-3 incorrectly shows Cyclone E in the variant column. It should show Cyclone V E. Issue 136679: I/O Features in Cyclone V Devices, Version 2013.06.21 Page 33 states the weak pull-up resistor is not supported on dedicated clock pins. This is incorrect, the weak pull-up resistor is supported on dedicated clock pins. Issue 138112: Cyclone V Device Datasheet, Version 1.3 2012.12.28 Table 5-24 shows the programmable IOE features and settings for Cyclone V devices. The pre-emphasis feature row indicates the assignments apply to allow values- 0 (enabled) and 1(disabled). This cell should be updated to 0(disable) and 1(enable). Issue 156380: Clock Networks and PLLs in Cyclone V Devices, Version 2013.05.06 There are two bullets for requirements when using automatic clock switchover, the first one is incorrect. It says: "Both clock inputs must be running." The purpose of automatic clock switchover is to switch between clocks if one stops running. The actual requirement is both clocks need to be running when the FPGA is configured. The bullet should say: "Both clock inputs must be running when the FPGA is configured." Issue 140192: I/O Features in Cyclone V Devices: Version 2013.6.21 Table 5-10 indicates the 3.3V input signal is not supported when VCCIO=2.5V in MuliVolt I/O Support. The table is incorrect and the 2.5V VCCIO can support a 3.3V input signal. Issue 138311: Cyclone V Device Datasheet: Version 3.4 Table 51 shows the value for t CO would be a maximum of 4us but this is incorrect, the maximum value for t CO should be 4ns. Issue 110591: Cyclone V Device Overview: Version 2012.12.28 Page 14, Figure 7 shows a M385 pin package is available, this is a typo and will be updated to a M386 pin package. Issue 98650: Volume 1, Chapter 4, Clock Networks and PLLs in Cyclone V Devices, Version 2012.12.28 The handbook currently states that External Feedback mode is supported on all Cyclone V PLLs, except on the corner fractional PLLs. This is incorrect. The handbook should state that External Feedback mode is supported on all Cyclone V PLLs, except on the strip fractional PLLs. Issue 92790: Volume 1, Chapter 5, I/O Features in Cyclone V Devices, Version 2012.12.28 Table 5-15: Modular I/O Banks for Cyclone V E A7 F672 package should have the following I/O counts: Bank 6A = 48 I/O pins available Bank 5B = 32 I/O pins available Issue 92829: Volume 1, Chapter 5, I/O Features in Cyclone V Devices, Version 2012.12.28 Table 5-23 should indicate that Current Strength 16, 8, 4 mA are available for 3.3V LVTTL I/O standards. Only 8, 4 mA is supported in HPS. Resolution Resolved Issues: Issue 67593: Volume 1, Chapter 5, I/O Features in Cyclone V Devices, Version 2.0 Statements implying VREF pins are available as user I/O pins removed in version 2012.12.28, VREF pins do not have user I/O pin functionality. Issue 41653: Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices, version 1.1 Configuration Schemes for Cyclone V Devices for AS (x1, x4) modes update to show AS configuration supports only 3.0 and 3.3V. Issue 41653: Device Interfaces and Integration Basics for Cyclone V Devices, version 1.1 This chapter has been integrated to the device handbook, volume 1. Active serial configuration has been updated to show support only for 3.0 and 3.3V VCCPGM, 1.8V is not supported. Issue 30381: Volume 2, Chapter 5, I/O Features in Cyclone V Devices, Version 1.1 Table 5-3 updated to show the 3.3-V LVCMOS I/O standard supports only a 2mA current strength.
