Why does my Deinterlacer II license fail?
Description Due to a problem in the Quartus® Prime Standard edition software version 16.1, designs containing the Deinterlacer II IP only generate a time-limited programming file. Resolution To resolve this problem in the Quartus Prime Standard edition software version 16.1, download and install the patch from the links below: Download the Quartus Prime version 16.1 Patch 0.04 for Linux (.run) Download the Quartus Prime version 16.1 Patch 0.04 for Windows (.exe) Download the Quartus Prime version 16.1 Patch 0.04 Readme (.txt) This problem is scheduled to be fixed in a future release.How do I address known software issues for Stratix V, Arria V and Cyclone V devices in the Quartus II software version 13.0 SP1?
Description There is a single patch available to address known software issues for Stratix® V, Arria® V, and Cyclone® V devices in the Quartus® II software version 13.0 SP1. This patch will be updated periodically with the latest software fixes. Check here periodically for updated files. Refer to the readme file for each device patch for the date the file was updated and information on the issues fixed in that patch. Resolution Download and install the Stratix V/Arria V/Cyclone V device patch 1.dp6 from the appropriate link below. You must install the Quartus II software version 13.0 SP1 before installing this patch. Note that you should not install any non-Stratix V/Arria V/Cyclone V patches on the Quartus II software version 13.0 SP1 after installing this patch. Patch 1.dp6 includes all fixes from the previously-released patch. You can install 1.dp6 over the previous device patch, but you do not need to install the previous device patch before installing patch 1.dp6. Download the version 13.0 SP1 (Subscription Edition) patch 1.dp6 for Windows (.exe) Download the version 13.0 SP1 (Subscription Edition) patch 1.dp6 for Linux (.tar) Download the Readme for the Quartus II software version 13.0 SP1 (Subscription Edition) patch 1.dp6 (.txt) To install a previously-released version of the Quartus II software version 13.0 SP1 Stratix V/Arria V/Cyclone V device patch, select the appropriate link below. Device patch 1.dp5 Download the version 13.0 SP1 (Subscription Edition) patch 1.dp5 for Windows (.exe) Download the version 13.0 SP1 (Subscription Edition) patch 1.dp5 for Linux (.tar) Download the Readme for the Quartus II software version 13.0 SP1 (Subscription Edition) patch 1.dp5 (.txt) Device patch 1.dp1 Download the version 13.0 SP1 (Subscription Edition) patch 1.dp1 for Windows (.exe) Download the version 13.0 SP1 (Subscription Edition) patch 1.dp1 for Linux (.run) Download the Readme for the Quartus II software version 13.0 SP1 (Subscription Edition) patch 1.dp1 (.txt) Related Articles Are there any updates to the 10GBASE-KR PHY IP core in Quartus II software version 13.0 SP1 dp1? Errata - Stratix V and Arria V timing model issues in the Quartus II software version 13.0 SP1 Why is my HPS DDR3 controller failing calibration? Why is the Cyclone V SoC Device SDRAM interface Vref pin voltage incorrect ? Why do I see random read errors using DDR2 SDRAM Controller with UniPHY/ DDR3 SDRAM Controller with UniPHY or LPDDR2 SDRAM Controller with UniPHY? Why do I see timing problems reported when using derive_pll_clocks using UniPHY-based memory controllers?Why do I see random read errors when using the DDR2, DDR3/DDR3L and LPDDR2 UniPHY IP on the Arria V GX/GT/SX/ST and Cyclone V E/GX/GT/SE/SX/ST devices?
Description On rare occasions, a problematic code word transition and DQSEN assertion which occur close to the rising edge of DQSIN may create a race condition causing distortion and/or glitch at the DQS delay chain output resulting in random read errors. Check the table below for the use cases affected based on the Quartus® II software version used.: Device Memory Controller Location Memory Interface Type Frequency (MHz) Quartus II Prior to v13.0sp1.dp5 Quartus II v13.0sp1.dp5 to v14.0.2 Quartus II v14.1 or later Cyclone® V & Cyclone V SoC HPS DDR2 & DDR3 f <= 400 Sensitive to DQS Glitch Not Affected Not Affected LPDDR2 f <= 333 Not Affected FPGA LPDDR2 f <= 333 Not Affected DDR2 & DDR3 f < 250 Not Affected 250 <= f < =400 Sensitive to DQS Glitch Arria® V & Arria V SoC HPS DDR2 & DDR3 f < 450 Sensitive to DQS Glitch Not Affected Not Affected f >= 450 Sensitive to DQS Glitch LPDDR2 f <= 400 Not Affected FPGA LPDDR2 f <= 333 Not Affected DDR2 & DDR3 f < 250 Not Affected f >= 250 Sensitive to DQS Glitch Resolution This issue was partially corrected in Quartus II software release version 13.0sp1 and fully resolved in version 14.1 and later, through bypassing the DQS delay chain. Regenerate the EMIF IP and recompile the design with Quartus II version 14.1 or later. For designs using Cyclone V and Cylcone V SOC, and customers who are unable to upgrade to Quartus II version 14.1, please contact Altera using mySupport. For designs using Arria V devices, refer to the following link: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd06222015_999.html Patches for related Quartus II software versions can be obtained from the following links: Quartus II 13.0SP1: Download the version 13.0 Service Pack 1 patch 1.dp6c for Windows (.exe) Download the version 13.0 Service Pack 1 patch 1.dp6c for Linux (.run) Download the Readme for the Quartus II software version 13.0 Service Pack 1 patch 1.dp6c (.txt) Quartus II 13.1.4: Download the version 13.1 Update 4 patch 4.64 for Windows (.exe) Download the version 13.1 Update 4 patch 4.64 for Linux (.run) Download the Readme for the Quartus II software version 13.1 Update 4 patch 4.64 (.txt) Quartus II 14.0.2: Download the version 14.0 Update 2 patch 2.18 for Windows (.exe) Download the version 14.0 Update 2 patch 2.18 for Linux (.run) Download the Readme for the Quartus II software version 14.0 Update 2 patch 2.18 (.txt)Why does the Frame Buffer II (4K Ready) Intel® FPGA IP drop my ancillary (user) packets?
Description Due to a problem with the Frame Buffer II (4K Ready) Intel® FPGA IP when Module is Frame Writer only is selected, you cannot change the Maximum ancillary packets field. That field, under the Memory section of the parameter editor, will be greyed out and not editable. Frame buffer in frame writer mode, default Ancillary packets = 0 This field defaults to 0 (zero), which will cause all ancillary packets (also known as User packets) to be dropped. Resolution To work around this problem, de-select Module is Frame Writer only, change the Maximum ancillary packets per frame to your desired setting, then re-select Module is Frame Writer only. Frame buffer with frame writer mode off and Ancillary packets entered Frame buffer in frame writer mode, note Ancillary packets = 3 This problem is fixed in the Intel® Quartus® Prime Software version 18.0.Error: set_port_property sets an illegal FRAGMENT_LIST for port unused_rx_parallel_data
Description Due to a problem in Intel® Quartus® II software version 13.1 update 3, you may see this error when using an Arria® V device Transceiver Native PHY instance with the “Enable simplified data interface" option selected and using the Rate Match FIFO and 8b10b encoder/decoder. Resolution To work around this problem, install the Intel® Quartus® II software version 13.1 Update 4 and then download and install patch 4.07 from the links below. Download the version 13.1 Update 4 patch 4.07 for Windows (.exe) Download the version 13.1 Update 4 patch 4.07 for Linux (.run) Download the Readme file for the Quartus II software version 13.1 Update 4 patch 4.07 (.txt) This problem is fixed starting with the Intel® Quartus® II software version 14.0.Why does my design have timing violations when compiled in the Quartus® II software version 15.0?
Description Due to a problem in the Quartus® II software version 15.0 Update 1 and Update 2 for Windows, your design may fail timing if it meets the following conditions: The target device is a Stratix® V or Arria® V GZ The design implements transceivers The Quartus® II software version 15.0 Update 1 and Update 2 for Linux is not affected by this problem. Resolution To work around this problem, download and install the appropriate patch for your Quartus® II version from the links below. You must install the Quartus® II software version before installing the patch. Download the version 15.0 patch 0.31 for Windows (.exe) Download the Readme for the Quartus II software version 15.0 patch 0.31 (.txt) Download the version 15.0.1 patch 1.10 for Windows (.exe) Download the Readme for the Quartus II software version 15.0.1 patch 1.10 (.txt) Download the version 15.0.2 patch 2.11 for Windows (.exe) Download the Readme for the Quartus II software version 15.0.2 patch 2.11 (.txt) This problem is fixed beginning with version 15.1 of the Quartus® Prime software.Why might the PCI Express signal detect feature fail at low temperatures on Arria® V GT and ST devices, and the link fails to train?
Description Due to an incorrect receiver common mode voltage (Rx Vcm) setting in Quartus® II software version 14.0 and earlier, the PCI Express® signal detect feature may fail at low temperatures on Arria® V GT and ST devices, and the link fails to train. The table below shows the Arria® device VCCR_GXB and Rx Vcm requirements. Device VCCR_GXB Voltage Rx Vcm Voltage Arria V GX, SX 1.1V/1.15V 0.65V Arria V GT, ST 1.2V 0.75V Resolution To work around this problem in Arria® V GT and ST devices, you can download and install the patch below and add the following Quartus® II Settings File (QSF) assignment for all PCI Express receiver channels in your design. Download the Quartus II software version 13.1 patch 0.110 for Windows (.exe) Download the Quartus II software version 13.1 patch 0.110 for Linux (.run) Download the Quartus II software version 13.1 patch 0.110 Readme file (.txt) set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P75V -to <pin_name> You must make the above assignment to all PCI Express receiver pins in your design, and you should not use wildcard characters (*) in your assignments. This problem has already been fixed in the Quartus® II software version 15.0.Internal Error: Sub-system: PVAFAM_VISITOR, File: /quartus/power/pvafam/pvafam_titan_atom_visitor_main.cpp, Line: 2002 Atom type not supported by PVA
Description Due to a problem in the Quartus® II software version 14.0 and earlier, when you use the Altera Advanced SEU Detection IP, Error Message Register (EMR) unloader IP, and/or Fault Injection Debugger IP in your design, you may see this error during the PowerPlay Power Analyzer (PPPA) or using Generate PowerPlay Early Power Estimator File. Resolution To work around this problem, download and install patch 0.109 from the links below. You must install Quartus® II software version 13.1 before installing this patch. Download the version 13.1 patch 0.109 for Windows (.exe) Download the version 13.1 patch 0.109 for Linux (.run) Download the Readme for the Quartus II software version 13.1 patch 0.109 (.txt) This problem is fixed beginning with the Quartus® II software version 14.1.Why does the EDCRC soft IP gate-level simulation netlist file for my Arria® V GX ES design not compile successfully in the ModelSim simulator?
Description During compilation in the Quartus® II software version 11.1 SP2, EDCRC soft IP is inserted for Arria® V GX ES devices. This soft IP contains an internal oscillator that does not have a simulation model. As a result, VHDL output (.vho) and Verilog HDL output (.vo) gate-level simulation netlist files may not compile successfully in the ModelSim software. You might see the following errors: Error: ModelSim Error: # ** Error: <design>.vho(<line number>): (vcom-1035) Formal port "ntrst" has OPEN or no actual associated with it. Error: ModelSim Error: # ** Error: <design>.vho(<line number>): (vcom-1035) Formal port "tdoutap" has OPEN or no actual associated with it. Error: ModelSim Error: # ** Error: <design>.vho(<line number>): (vcom-1141) Identifier "arriav_oscillator" does not identify a component declaration. Resolution A patch is available to work around this limitation in the Quartus II software version 11.1 SP2. Download and install Patch 2.12 from the appropriate link below. After installing the patch, you can use a variable in the quartus.ini file in your project directory to control compilation. To generate a gate-level simulation netlist, create or edit a quartus.ini file in your project directory and add the following line: sgn_add_av_es_soft_ip=off This variable disables the auto-insertion of EDCRC soft IP and allows the gate-level simulation netlist file to compile successfully in the ModelSim software. However, programming files will not be generated. To generate programming files, you must remove the variable from the quartus.ini file. Download the following patch: Version 11.1 SP2 patch 2.12 for Windows (.exe) Version 11.1 SP2 patch 2.12 for Linux (.tar) Readme for the Quartus II software version 11.1 SP2 patch 2.12 (.txt)Arria V and Arria V SoC Core-to-Periphery (C2P) Timing Miscorrelation
Description There is a timing model miscorrelation in a subset of Core-to-Periphery (C2P) data paths which might result in an incorrect FPGA output for designs that have low setup slack in the affected paths. This affects Arria® V and Arria V SoC designs (excluding Arria V GZ devices) using the affected output pins in the top and/or bottom I/O banks. This issue does not affect Periphery-to-Core (P2C) transfers, I/O banks on the right, transceivers and hard memory controller. Resolution Checking affected pins used in design If your design targets Arria V or Arria V SoC devices (excluding Arria V GZ devices), please refer to the ArriaV_PinList Excel file for a list of affected pins indicated in red text. If your design uses any of the affected pins, rerun timing analysis using the available timing model patch to reflect the actual timing margin in your design as described below. Rerun Timing Analysis in the Updated Software Version If your designs target Arria V or Arria V SoC devices (excluding Arria V GZ devices), or if you are debugging a timing-related issue, re-run timing analysis using the available timing model patch as follow: Back up the design database. Open the design in the earlier Quartus® II software version, and then export the database. On the Project menu, click Export Database. When you are prompted, export the database to the suggested export_db directory. Start Quartus II software with the installed timing model patch. Open the project. When you are prompted whether to overwrite the older database version, click \'Yes’, and import the database from the export_db directory. Run the TimeQuest timing analyzer on the design. If there are timing violations, recompile with the timing model patch to close timing on the design. Steps to Improve Timing Closure (UniPHY Quarter Rate DDR3) To improve timing closure in quarter-rate UniPHY DDR3 interfaces on Arria V or Arria V SoC devices, Altera recommends changing the phase of the clock domain immediately preceding the periphery clock domain. Follow these steps to ease timing closure in using the timing model patch. Create a new text file and name it ‘quartus.ini’ Save this file in your home directory.The below are sample home directories, but can be different on your computer based on your environment variables. For Windows : C:\Users\<username> For Linux : /home/<username> Insert the following INI command in the quartus.ini file to increase the setup relationship by the specified amount of phase value. uniphy_av_hr_clock_phase = <phase_value> The legal <phase_value> to be used are in the decremental fashion of 22.5° from the default value of 360° (i.e the <phase_value> to be inserted in the quartus.ini file are 337.5°, 315°, 292.5°, 270°, etc). For example: Inserting uniphy_av_hr_clock_phase=337.5 will increase the default setup relationship by 22.5°. Inserting uniphy_av_hr_clock_phase=315 will increase the default setup relationship by 45°. Inserting uniphy_av_hr_clock_phase=292.5 will increase the default setup relationship by 67.5°. Inserting uniphy_av_hr_clock_phase=270 will increase the default setup relationship by 90°. Regenerate the UniPHY IP, recompile the design and ensure timing closure. Steps to Improve Timing Closure (LVDS Tx) To improve timing closure in LVDS Tx on Arria V or Arria V SoC devices, Altera recommends changing the phase of the clock domain immediately preceding the periphery clock domain. Follow these steps to ease timing closure using the timing model patch*. Create a new text file and name it ‘quartus.ini’ Save this file in your project directory. Insert the following INI command in the quartus.ini file to turn on the phase shifting feature. This by default will increase the setup relationship of the transfers by 400ps. av_lvds_c2p_sclk_phase_shift_en = on Delete the db and incremental_db directories in the project, recompile the design and ensure timing closure. If timing is not met after using the command above, try using other phase shift values by adding the following command in the same quartus.ini file and repeat step 4. av_lvds_c2p_sclk_phase_shift = <phase_value> Note: The phase value is in ps which must not be included in the ini variable. To update the timing model, download and install the appropriate the patch for your version of the Quartus II software. Download the version 13.0 Service Pack 1 patch 1.dp6c for Windows (.exe) Download the version 13.0 Service Pack 1 patch 1.dp6c for Linux (.run) Download the Readme for the Quartus II software version 13.0 Service Pack 1 patch 1.dp6c (.txt) Download the version 13.1 Update 4 patch 4.64 for Windows (.exe) Download the version 13.1 Update 4 patch 4.64 for Linux (.run) Download the Readme for the Quartus II software version 13.1 Update 4 patch 4.64 (.txt) Download the version 14.0 Update 2 patch 2.18 for Windows (.exe) Download the version 14.0 Update 2 patch 2.18 for Linux (.run) Download the Readme for the Quartus II software version 14.0 Update 2 patch 2.18 (.txt) Download the version 14.1 Update 1 patch 1.18 for Windows (.exe) Download the version 14.1 Update 1 patch 1.18 for Linux (.run) Download the Readme for the Quartus II software version 14.1 Update 1 patch 1.18 (.txt) Download the version 15.0 Update 1 patch 1.04 for Windows (.exe) Download the version 15.0 Update 1 patch 1.04 for Linux (.run) Download the Readme for the Quartus II software version 15.0 Update 1 patch 1.04 (.txt) The timing model update will be included version 15.0 Update 2 of the Quartus II software.