Why do I see timing violations in 1G/10G and 10GBASE-KR PHY FPGA IP?

Description

Due to an issue in 1G/10G and 10GBASE-KR PHY FPGA IP, Quartus® Prime Standard Edition Design Software is unable to generate SDC file along with the IP files.

Resolution

As a workaround, download the file below.

Check the following parameter values in the downloaded .sdc file and modify as per the design, if required:

1. num_channels
2. period_10g
3. period_1g
4. period_mgmt
5. path_project