How can I support legacy SFP modules with Agilex™ 5 FPGA and Agilex™ 3 FPGA GTS receivers?
Description Altera® Agilex™ 5 FPGA and Agilex™ 3 FPGA device GTS receivers cannot tolerate 2V pk-pk signals from legacy SFP modules. Resolution You can support legacy SFP modules by adding inline 6dB RF attenuators in between the SFP module and the Agilex™ 5 FPGA and Agilex™ 3 FPGA device GTS receiver. You must also power sequence the SFP module, ensuring that it powers up after the FPGA is configured. The Agilex™ 5 FPGA and Agilex™ 3 FPGA device GTS equalizer in Auto Adaptation mode should open the RX eye for reduced amplitude SFP+ signals. Altera recommend that you perform signal integrity analysis of your interface.Internal Error: Sub-system: QCU, File: /quartus/comp/qcu/qcu_qis_utility.cpp, Line: 1673
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 or earlier, you might see this internal error when you run Start Standard to Pro Lint. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 25.1.1, download and install the patch below. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.3.1.Why does the Synchronous FIFO Parameterizable Macro (sync_fifo) incorrectly output all zeroes data after being empty?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1 or earlier, you might see that the first output data from the FIFO after the FIFO has been empty is incorrectly set to zero. This problem occurs when using the Synchronous FIFO Parameterizable Macro (sync_fifo) in show-ahead mode. Resolution To work around this problem, instantiate the FIFO FPGA IP instead of the Synchronous FIFO Parameterizable Macro. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why is there a mismatch in the PFC width between the theory calculation and the hardware measurement in the GTS Ethernet Hard IP design?
Description You might observe a mismatch in the PFC width between the theory calculation and hardware measurement at max PFC quanta. This is due to the alignment marker (AM) pulse window within the PCS data, which is causing this variation. Resolution Estimating the deviation of the PFC width from the expected value is not feasible. Quanta variation is not quantifiable, and the variation is expected. There is no plan to fix this problem.Why does HPS Coresight Trace Clock detection fail with Quartus® Prime Pro version 25.3?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, the 'tpiu_trace_ctl' port is now tied to 0, causing a failure that did not occur when the port was left unconnected in previous versions. Resolution To work around this problem, perform the following steps: Run the IP Generation stage of the Quartus® compilation flow. Modify the generated file from IP Generation: Change in file: <ip_path>/hps_subsys/agilex_hps/intel_sundancemesa_hps_100/synth/agilex_hps_intel_sundancemesa_hps_100_*.v Original: Modified: 3. Continue the Quartus® Compilation flow from Analysis & Synthesis onward. (Note: Do not run the IP Generation stage again) This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.Why is the o_rx_pfc port enabled for longer durations than expected with 10/25GE designs using the GTS Ethernet Hard IP with Priority Flow Control (PFC) enabled?
Description When operating the GTS Ethernet FPGA Hard IP for 10/25GE with PFC enabled, the o_rx_pfc port stays asserted beyond the configured quanta time whenever all of the following conditions are fulfilled: During the processing state of “PAUSE”, if new oversized frame is received Frame size larger than configured “maximum frame size” during the design generation in GTS Ethernet Hard IP. “Enforce maximum frame size” option is enabled in GTS Ethernet FPGA Hard IP GUI. The typical effect is an extended pause prior to resuming packet flow Resolution When enabled the “Forward RX pause requests” option in GTS Ethernet Hard IP GUI, disable the “enforce maximum frame size” option. There is no plan to fix this problem.Why are the SDC constraints for link clocks generated by the GTS JESD204B FPGA IP inaccurate?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3, you may observe incorrect SDC constraints for link clocks generated by the GTS JESD204B FPGA IP. Resolution To work around this problem, update the value of period in the following constraints in ip/intel_jesd204b_gts_phy_<version>/synth/j204b_gts.sdc: create_clock -name "rxlink_clk" -period <period>ns [get_ports rxlink_clk] create_clock -name "txlink_clk" -period <period>ns [get_ports txlink_clk] where <period> is the calculated value of 1/(data rate/40). This problem has been fixed in the Quartus® Prime Pro Edition software version 24.3.1.Internal Error: Sub-system: QPR, File: /quartus/comp/qpr/qpr_route_mask_generator_details.h, Line: 594
Description Due to a problem in Quartus® Prime Pro Edition Software versions 25.1 and 25.1.1, you might see this internal error at the fitter stage when compiling a Partial Reconfiguration (PR) implementation that uses a global reset on fast input/output registers. The base revision compiles successfully, the error occurs only in PR implementations with this global reset usage. Resolution To work around this problem in the Quartus® Prime Pro Edition Software v25.1.1 or v25.1, download and install the patches below. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.3.1.Why does the Nios® V processor that applies fast JTAG UART driver stop (stuck in a loop) when the JTAG UART terminal is not active?
Description Due to a problem in the Board Support Package Editor of Quartus ® Prime software, the JTAG UART driver for fast implementation might get stuck in a loop for any Nios ® V processor designs, when JTAG UART terminal is not active. This problem has been present since: Quartus ® Prime Pro Edition software version 21.3 Quartus ® Prime Standard Edition software version 22.1 It is because the JTAG UART IP is initialized before the Nios ® V processor initialization in alt_sys_init.c. For example: void alt_sys_init( void ) { ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); INTEL_NIOSV_M_INIT (NIOS, nios); } Resolution To work around this problem, update the alt_sys_init.c to initialize the Nios ® V processor first. void alt_sys_init( void ) { INTEL_NIOSV_M_INIT (NIOS, nios); ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); } This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime software. Additional Information Refer to Embedded Peripherals IP User Guide [titled as JTAG UART Core - Driver Options: Fast vs. Small Implementations] for more information about the JTAG UART driver for fast (non-blocking) and slow (blocking) implementation. Related Article NIOSV firmware stuck when juart-terminal is not open for the print messages.Training (AN/LT) IP with ECC enabled designs?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1, you may see linkup problem for multi-port GTS Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) IP designs when ECC is enabled. Resolution Currently there is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.
