Why do I see a generation failure with simulation enabled, or a compilation failure, in the Integrated PHY Dual-Simplex Serial Loopback design example with TX Clock Switching?

Description

Due to a problem in the Quartus® Prime Pro Edition software version 26.3, you may see the following problems when generating or compiling the Integrated PHY Dual-Simplex Serial Loopback design example with TX Clock Switching enable:

1. Generation failure when simulation is enabled
   When you enable simulation in the design example, generation fails. There is currently no workaround for this problem.
   This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.

1. Compilation failure when simulation is disabled
   The gxb_tx_refclk_cmd_bus_in[*] ports are missing from the shared_clocks list of the TX QHIP_IP_PROPERTY assignment in the .qsf file. Because of this, compilation fails with the following error:
   Error (26050): IP instance port name sdi_tx_inst|gxb_tx_refclk_cmd_bus_in[n] for DR_SHARED_CLOCK assignment in dual simplex/reconfiguration group dr_top is not allowed.
   
   To fix this compilation failure, follow the workaround in the Resolution section.

Resolution

To work around compilation problem, user needs to add the gxb_tx_refclk_cmd_bus_in[0] to gxb_tx_refclk_cmd_bus_in[9] ports to the shared_clocks list of the TX QHIP_IP_PROPERTY assignment in qsf file.

 Example:

1. "shared_clocks" : ["system_pll_clk", "system_pll_lock", "tx_pll_refclk", "gxb_tx_refclk_cmd_bus_in[9]", "gxb_tx_refclk_cmd_bus_in[8]", "gxb_tx_refclk_cmd_bus_in[7]", "gxb_tx_refclk_cmd_bus_in[6]", "gxb_tx_refclk_cmd_bus_in[5]", "gxb_tx_refclk_cmd_bus_in[4]", "gxb_tx_refclk_cmd_bus_in[3]", "gxb_tx_refclk_cmd_bus_in[2]", "gxb_tx_refclk_cmd_bus_in[1]", "gxb_tx_refclk_cmd_bus_in[0]"]}}

2. Save the file and recompile the design.