Why do I see this warning message after enabled Transceiver Toolkit Debugging Features in Serial Design ?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1.1, you will observe below. “warning check failed! > warning: no path is found satisfying assignment" “set_max_skew -from get_registers auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t1_fifo|in_wr_ptr_gray -to get_registers auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t1_fifo|write_crosser|sync.u|din_s1 -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 - This assignment will be ignored.” It happen when enabled Transceiver Toolkit Debugging Features in Serial Design. This problem happens due to undefined the path of the dc_fifo.sdc. Resolution This problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.Why am I seeing High Severity DA warning Multiple Clock Domains Driving a Synchronizer Chain after I enabled Transceiver Toolkit Debugging Features in Dual-Simplex Parallel loopback with external and without VCXO Design Example ?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1.1 you may see there is different clock domains driven in a synchronizer chain causing high severity DA warning in report compilation Resolution This problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.
What are the valid bits of the reconfiguration address bus to specify the selected channel when enabling the "Share reconfiguration Interface" option for the Transceiver Native PHY Arria® 10 FPGA/Cyclone® 10 GX FPGA IP
Description Due to a problem in the Transceiver Native PHY Arria® 10 FPGA/Cyclone® 10 GX FPGA IP information window, when enabling the "Share reconfiguration Interface" option, there is an incorrect message that upper[n:9] address bits of the reconfiguration address bus specifies the selected channel. According to the Arria® 10 Transceiver PHY User Guide, when you turn on the "Share reconfiguration Interface" option, the Transceiver Native PHY IP presents a single Avalon memory-mapped interface slave interface for dynamic reconfiguration for all channels. In this configuration, the upper [N-1:10] bits of the reconfiguration address bus specify the selected channel. The channel numbers N are binary encoded. Address bits [9:0] provide the register offset address within the reconfiguration space for a channel. ResolutionHow do I enable the electrical idle feature in the E-Tile Transceiver Native PHY Agilex® 7 FPGA IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 22.1 and earlier, this feature is currently not supported. Resolution The problem has been fixed starting with Quartus® Prime Pro Edition software version 24.3.Why isn’t there any PLLs usage if I compile the project with the Stratix® 10 FPGA E-tile transceiver channels ?
Description This is an expected behaviour. You will see "Total PLLs" usage is 0 if you only instantiate Intel® Stratix® 10 FPGA E-tile transceiver channels in the design. The Stratix® 10 FPGA E-tile transceiver channel phase-locked loop (PLL) would not be counted in the total PLLs summary. For example, if you use Stratix® 10 device 1ST280EY2F55, and instantiate four E-tile transceiver channels. After compilation, you will still see the “Total PLLs 0/64(0%)” in the flow summary of the compilation report. Resolution All PLLs shown in the compilation report are contributed by the Stratix® 10 IOPLL and H-tile transceiver PLLs. For Stratix® 10 device 1ST280EY2F55, the total 64 PLLs consist of 24xIOPLLs, 8xfPLLs of H-tile, 8xATX PLLs of H-tile transceiver, and 24 CDR PLLs of H-tile transceiver. Stratix® 10 FPGA E-tile transceiver channel PLLs are not counted. The problem has been fixed starting with Quartus® Prime Pro Edition software version 19.3.Why is the manual lock to reference mode of the GTS transceivers in Agilex® 5 FPGA not working as expected?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1 and earlier, the manual lock to reference mode of the GTS transceivers in Agilex® 5 FPGA does not work as expected. Resolution For a workaround, users will need to follow the following steps to enable the manual lock to reference mode to function properly. Write 0x1 to 0x818 [0] for Software Reset Controller(SRC) to ignore the CDR LTD status. Write 0x1 to both 0x91680 [24] and 0x91680 [28] for enabling LTR mode Write 0x1 to both 0x91580 [30] and 0x91580 [31] for enabling RX parallel data in manual LTR mode The manual LTR mode will only work when adaptation is set to manual. This problem is fixed beginning with the Quartus Prime Pro Edition software version 25.3.Why do I see link failure after a few resets when the GTS Transceiver PMA link is placed under internal serial loopback mode?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, if you are selecting either of the two below example designs and try to enable the internal serial loopback mode, you will see link failure, especially after one or multiple resets. The impacted example designs are: 1 x 1G PMA Direct Mode (System PLL Clocking) with Custom Cadence 1 x 3.125G PMA Direct Mode (System PLL Clocking) with Custom Cadence This is due to the default setting of the RX Equalizer parameters (VGA gain, DFE Tap 1, and High Frequency Boost) value in the example design are not compatible during the internal serial loopback mode. Resolution To overcome this problem, you can follow the section of the GTS Transceiver PHY user guide, section 3.14.2.2, to store and restore the RX Equalizer settings. The original RX equalizer parameter value can be restored after you disable the internal serial loopback for your GTS Transceiver PMA link. This problem is fixed beginning with the Quartus Prime Pro Edition software version 25.3.Why does the o_tx_pll_locked signal of the GTS transceivers show an asserted state when there is no input reference clock for Agilex® 5 FPGA devices in the Quartus® Prime Pro Edition Software version 24.1 and 24.2?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 24.1 and 24.2, the o_tx_pll_locked signal does not reflect the correct status of the TX PLLs in the GTS transceiver. This causes the o_tx_pll_locked signal to be incorrectly asserted without an input reference clock. Additionally, when a loss of reference clock occurs, the o_tx_pll_locked status signal will not go low. This deviates from the expected behavior described in section 3.8.9 of the GTS Transceiver PHY user guide. The only supported condition is ensuring the input reference clock is always present. Resolution This problem is fixed beginning with the Quartus Prime Pro Edition software version 25.3.1.Why is data packet loss due to CRC error observed in Agilex® 5 and Agilex® 3 TSN XCVR SGMII 1G mode?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, when running the TSN - SGMII XCVR System for the Agilex® 5 FPGA E-Series Premium Development Kit, you may observe data packet loss in the TX direction for a 1G SGMII configuration with the TSN transceiver PHY. This issue is not seen with 10m,100m, and 2.5G configurations. Resolution To work around this problem, some changes in the software and hardware design files are required. Software Changes: 1. Change link.speed1000 parameter value from XGMAC_CONFIG_SS_1000_GMII to XGMAC_CONFIG_SS_2500_GMII in the following file. <user_path>/src/sw/agilex5_dk_a5e065bb32aes1-gsrd-rootfs/tmp/work-shared/agilex5_dk_a5e065bb32aes1/kernel-source/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c mac->link.speed10 = XGMAC_CONFIG_SS_10_MII; mac->link.speed100 = XGMAC_CONFIG_SS_100_MII; -mac->link.speed1000 = XGMAC_CONFIG_SS_1000_GMII; +mac->link.speed1000 = XGMAC_CONFIG_SS_2500_GMII; mac->link.speed2500 = XGMAC_CONFIG_SS_2500_GMII; Hardware Design Changes: 1. Replace the existing input with 2'b00 for the signals below in the file below: <user_path>/applications.fpga.soc.agilex5e-ed-tsn-config3/src/hw/ghrd_agilex5_top.v .phy_0_gmii8b_mac_speed_export (2'b00), ... .phy_0_xcvr_mode_export (2'b00), Additional Information There is no workaround currently, and there is no plan to fix this problem.