What are the valid bits of the reconfiguration address bus to specify the selected channel when enabling the "Share reconfiguration Interface" option for the Transceiver Native PHY Intel® Arria® 10/Cyclone® 10 GX FPGA IP

Description

Due to a problem in the Transceiver Native PHY Intel® Arria® 10/Cyclone® 10 GX FPGA IP information window, when enabling the "Share reconfiguration Interface" option,  there is an incorrect message that upper[n:9] address bits of the reconfiguration address bus specifies the selected channel.

 

According to the Intel® Arria® 10 Transceiver PHY User Guide, when you turn on the "Share reconfiguration Interface" option, the Transceiver Native PHY IP presents a single Avalon memory-mapped interface slave interface for dynamic reconfiguration for all channels. In this configuration, the upper [N-1:10] bits of the reconfiguration address bus specify the selected channel. The channel numbers N are binary encoded.

 

Address bits [9:0] provide the register offset address within the reconfiguration space for a channel.

 

Resolution

This problem is scheduled to be fixed in a future release of the Intel Quartus® Prime Pro Edition Software.