Error(22465): Refclk frequency of IP port '<pma_direct_multirate_ip_path>|tx_pll_refclk_link_xcvr0_prof0' (156.25 MHz) does not match the refclk frequency of system clock IP port '<ftile_refclk_sys_pll_clocks_ip_path>|out_fht_cmmpll_clk_0' (100.00 MHz)

Description

Due to a bug in the Quartus® Prime Pro software version 26.1 and earlier. you may see an error similar to the above when compiling an PMA Direct PHY Multirate IP configured for F-Tile FHT channels on Agilex® 7 FPGA Devices. You may see this error even though the FHT frequencies in your PMA Direct PHY Multirate IP and F-Tile reference and System PLL Clocks IP are matched.

The problem is caused by the Quartus Prime Pro software erroneously referencing a disabled FGT reference clock pin that is set to 100MHz by default in the F-Tile reference and System PLL Clocks IP.

Resolution

To work around this problem, you can enable the FGT REFCLK in the F-Tile reference and System PLL Clocks IP, change the frequency from 100MHz to match your design (156.25MHz in this case), and disable the FGT REFCLK again.

This problem will be fixed in a future version of the Quartus Prime Pro software.