Why does the DisplayPort example design fail to generate in Quartus® Prime Pro Edition Software version 26.1?
Description Due to a problem in Quartus® Prime Pro Edition Software version 26.1, you may see a software build failure when generating the DisplayPort FPGA IP Design Example. In this condition, the generated Nios® V software build fails in debug.c because the load_resolutions() call passes modes_found instead of &modes_found. You may see an error similar to the following: debug.c:486:94: error: passing argument 4 of 'load_resolutions' makes pointer from integer without a cast note: expected 'int *' but argument is of type 'int' Error: Failed to generate example design Resolution To work around this problem, modify debug.c line 486 either in the installed source or in the generated example design, and then regenerate or rebuild the design. Change: load_resolutions (1, mode_param_array, &dsc_data_pps_parameters, modes_found); to: load_resolutions (1, mode_param_array, &dsc_data_pps_parameters, &modes_found); This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.
Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IPWhy is the Avalon MM interface optimized away when using the SDI Audio Embed or SDI Audio Extract IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, the SDI Audio Embed IP and SDI Audio Extract IP might show incorrect behaviour when the generated IP name is audio_embed or audio_extract. In this condition, the affected output ports are left undriven and connected to the default value gnd, you will see messages similar to those shown below: Output port "reg_waitrequest" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_waitrequest" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Resolution To work around this problem, use a different IP name to avoid a naming that conflicts with the generated HDL module naming used by the Quartus® Prime Pro Software for the SDI Audio Embed or SDI Audio Extract IP. For example: Do not name the SDI Audio Embed IP as audio_embed. Do not name the SDI Audio Extract IP as audio_extract. Regenerate the IP after renaming it to a non-conflicting name. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.How can the generation of the iossm_bf_cpu_cpu.tr file be disabled when simulating the Stratix® 10 DDR4 IP?
Description Due to a problem in the Quartus® Prime Software versions 18.0 and 18.1, a large trace file called iossm_bf_cpu_cpu.tr is generated when you simulate a design containing the Stratix® 10 DDR4 IP. Resolution To disable the generation of the iossm_bf_cpu_cpu.tr file, download and install the Quartus® Prime Software version 18.1 patch 0.21. > Download the Readme (.txt) for the version 18.1 patch 0.21 > Download the version 18.1 patch 0.21 for Windows (.exe) > Download the version 18.1 patch 0.21 for Linux (.run)Error: add_fileset_file: No such file C:/intelFPGA_pro/21.1/ip/altera/sld/st/intel_st_debug_if/cadence/intel_st_dbg_if_csr_h.sv
Description Due to a problem in the JTAG-Over-Protocol Intel® FPGA IP, using the Intel® Quartus® Prime Pro Edition Software version 21.1 and 21.2 you may see an error message similar to the following when generating the HDL code with the option Create simulation model= Verilog or VHDL. Error: add_fileset_file: No such file C:/intelFPGA_pro/21.1/ip/altera/sld/st/intel_st_debug_if/cadence/intel_st_dbg_if_csr_h.sv while executing "add_fileset_file $current_sim/intel_st_dbg_if_csr_h.sv SYSTEM_VERILOG PATH $current_sim/intel_st_dbg_if_csr_h.sv $attr" (procedure "add_rtl_files" line 25) invoked from within "add_rtl_files sim" (procedure "sim_callback" line 2) invoked from within "sim_callback intel_st_dbg_if_top" Resolution A patch is available to work around this problem for the Intel® Quartus® Prime Pro Edition Software version 21.1 and 21.2. Download and install the patch from the appropriate link below. Download patch Intel® Quartus® Prime Pro Edition 21.1 Patch 0.40 for Windows (.exe) Download patch Intel® Quartus® Prime Pro Edition 21.1 Patch 0.40 for Linux (.run) Download the Readme for Intel® Quartus® Prime Pro Edition 21.1 Patch 0.40 (.txt) Download patch Intel® Quartus® Prime Pro Edition 21.2 Patch 0.13 for Windows (.exe) Download patch Intel® Quartus® Prime Pro Edition 21.2 Patch 0.13 for Linux (.run) Download the Readme for Intel® Quartus® Prime Pro Edition 21.2 Patch 0.13 (.txt) This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.Why does the DisplayPort IP design example fail to generate a programming file when using the Quartus® Prime Pro Edition Software v19.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software v19.1, designs that use the Nios® II/e processor core without a valid Nios® II processor license will fail to generate programming files even though the design compilation is successful. The DisplayPort IP design example uses the Nios II/e processor core. Hence, it will be impacted by this problem. Resolution To work around this problem in the Quartus® Prime Pro Edition Software v19.1, install the patch 0.02 below and regenerate the DisplayPort IP design example: This problem is fixed starting with the Quartus Prime Pro Edition Software v19.2.Internal Error: Sub-system: RTM, File: /quartus/tsm/rtm/rtm_atom_mgr.cpp, Line: 2046
Description Due to a problem in Intel® Quartus® Prime Pro Edition software version 19.1, you may see this Internal Error in a fitter stage for designs targeting Intel® Stratix® 10. Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition software version 19.1. Download and install Patch 0.28 from the appropriate link below. Download patch 0.28 for Windows (.exe) Download patch 0.28 for Linux (.run) Download the Readme for patch 0.28 (.txt) This problem has been fixed beginning with version 19.3 of the Intel® Quartus® Prime Pro Edition software.Why does the AXI read transaction ID (RID) value change during a read data transfer when using the Intel® Stratix® 10 MX HBM2 controller?
Description Due to a problem in the Intel® Stratix® 10 MX HBM2 controller when using the Intel Quartus® Prime Pro Edition software versions 20.4 or earlier, you may see that the AXI master returns a different value for the read address ID axi_0_0_rid signal if the read burst length axi_0_0_arlen signal is greater than 2. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition software versions 20.4 or earlier, Download hbm_burst_rid_fix.zip file and replace the following encrypted files from the existing ones. ./sim_mentor/altera_axi_ufi_axi_burst_ctrl.sv // Copy to /ip/ed_synth/ed_synth_hbm_0_example_design/altera_axi_ufi_adapter_191/sim/mentor/ ./syn_quartus/altera_axi_ufi_axi_burst_ctrl.sv // Copy to /ip/ed_synth/ed_synth_hbm_0_example_design/altera_axi_ufi_adapter_19 This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.1.Why is M20K dual-port RAM data corrupted in the first read operation or the first write operation when using rd_addressstall or wr_addressstall in the Intel® Stratix® 10 device?
Description Due to a problem of the Intel® Quartus® Prime Pro software version 18.1.1 and later, M20K dual-port RAM data may be corrupted in the first read operation or the first write operation when using rd_addressstall or wr_addressstall in the Intel Stratix® 10 device. This problem is observed only when rd_addressstall or wr_addressstall is initially high from the beginning of user mode and is kept high until the 1st read operation or the 1st write operation. Resolution Toggle rd_addressstall to low with a valid read address for at least one read clock cycle when using rd_addressstall Toggle wr_addressstall to low with a valid write address for at least one write clock cycle when using wr_addressstall A patch is available to fix this problem in the Intel® Quartus® Prime software version 19.3 Download patch Intel Quartus Prime 19.3 Patch 0.57 for Windows (.exe) Download patch Intel Quartus Prime 19.3 Patch 0.57 for Linux (.run) Download the Readme for Intel Quartus Prime 19.3 Patch 0.57 (.txt) This problem has been fixed since the Intel Quartus Prime Pro software version 20.3.Why do I have functional errors in my Intel® Stratix® 10 design?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 18.1 and earlier, you may see functional errors in your Intel® Stratix® 10 design. This problem occurs when 7 or 8 inputs LUTs are incorrectly optimized during pin rotation. Resolution To work around this problem download and install the patch for the Intel Quartus Prime Pro edition software version 18.0 Update 1 or 18.1 Download and install Patch 1.44 for 18.0 Update 1 from the appropriate link below. Download the version 18.0 Update 1 patch 1.44 for Windows (.exe) Download the version 18.0 Update 1 patch 1.44 for Linux (.run) Download the Readme for the Intel Quartus Prime Pro edition software version 18.0 Update 1 patch 1.44 (.txt) Download and install Patch 0.33 for 18.1 from the appropriate link below. Download the version 18.1 patch 0.33 for Windows (.exe) Download the version 18.1 patch 0.33 for Linux (.run) Download the Readme for the Intel Quartus Prime Pro edition software version 18.1 patch 0.33 (.txt) This problem is fixed beginning with the Intel Quartus Prime Pro Edition software version 18.1 Update 1 For designs that are already in production, download and run the script lut8_iobuf_qsh_v3.tcl to check if the compiled design is affected by this problem. Command -> quartus_sh -t lut8_iobuf_qsh_v3.tcl -project <project name> -revision <revision name> -npaths 100 -debug 0 -verbose -check_lutmasks -vo_file simulation/modelsim/<revision name>.vo Output -> lut8check.rpt, iobuf.rpt, paths.csv lut8check.rpt reports the LUTs impacted, if this report contains "Found 0 LUTs with potentially incorrect bit settings" then the compiled design is safe. If the design is affected then the LUTs with this problem will be listed in the report. iobuf.rpt and paths.csv report the paths that are affected by the timing model changes described in the KDB Is the Intel® Stratix® 10 timing model correct in the Intel® Quartus® Prime Pro Edition software versions 18.0 Update 1 and 18.1?