Cyclone 10 LP's Extended Industrial parts
[Question] Customer have questions about Cyclone 10 LP's Extended Industrial (Tj = -40degC to 125degC) in the Product Catalog at the following URL. https://www.intel.com/content/www/us/en/content-details/730595/altera-product-catalog.html What is part number of Extended Industrial of "10 CL010YM164I7 G" as part number of Normal Industrial? What should the customer do if they want to check the power consumption by EPE(Early Power Estimator)? How can the customer design with Extended Industrial part if they want to compile with Quartus? Best Regards
Cyclone IV E – PLL Power Track Width Recommendation Clarification
Hi, I am working on a design that uses the Cyclone IV E FPGA, and I’ve been following the Altera/Intel board design guidelines for PLL power routing. The document recommends using a minimum 20 mil trace width for the PLL power supply routing. Due to space constraints on our PCB, we have routed the PLL supply net as follows: From the ferrite bead to the FPGA cutout: 20 mil trace width After the cutout region leading into the FPGA power pin area: reduced to 6 mil trace width My questions are: Is it acceptable to reduce the PLL power trace width from 20 mil to 6 mil after the cutout region? If not, what issues might arise due to this narrower trace? I have attached a snapshot from the guideline for reference. Requesting your comments and guidance on whether this implementation is safe or if the narrower section could cause problems with PLL performance. Thanks in advance!
Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered
Hello, I would like to confirm the voltages allowed on the Agilex 7 F series Transceiver I/O (the Transceiver Data lanes and the REF_CLK inputs) during power-up or when the Agilex and its transceivers tiles are not powered. For example, I'd like to know if a scenario where Agilex interfaces to an external PCIe host that may drive PCIe clock to the Agilex Transceiver REF_CLK input before it's powered/while it's powering up is acceptable. The requirements for the Agilex GPIO, HPS_IO, and SDM_IO during powerup/when unpowered are clear to me from below documents but not the Transceiver I/O. I don't see any constraints specified for the Transceiver I/O during powerup unless I'm missing it. Can you please confirm this for me, or point me to where this is documented? If it matters, I am interested specifically in F-tile. The A692 Power Sequencing Considerations app note states the below: So it's clear for Cyclone GX, Arria 10, and Stratix 10 L/H tiles that no activity is allowed (with exception of 1.0 Vp-p on Stratix 10) on transceiver I/O during power-up but Agilex is not mentioned in this section. The Agilex 7 General-Purpose I/O User Guide states the following: Table 3: GPIO pin voltage must not exceed VCCIO_PIO or 1.2V, whichever is lower Table 22: HPS I/O pin voltage must not exceed VCCIO_HPS. Table 29: SDM I/O pin voltage must not exceed VCCIO_SDM. I don't see any mention of similar constraint for Transceiver I/O. The Agilex 7 Power Management User Guide states the following: Again, I see all I/O other than Transceiver I/O mentioned. Thanks!MAX 10 FPGA POR trip Levsl and tRAMP
I am intending to use a 36 pin count dual power supply MAX 10 part for a lower power application. From Fig 3 of UG-M10PWR (pasted below), nStatus is asserted when POR trip level is met within tRAMP. The battery for my application may have a longer ramp up time than tRAMP (10 msec for my part). What is the consequence of this. Will device not come out of reset if tRAMP condition is not met? Are there any workarounds for this?Agilex 9 power
We started a new design based on the Agilex 9 AGRW027R28A2I2V Our power designer has the following question: "Can the VCCA_AXA0_1P8 and VCCA_AXA1_1P8 be powered by the same voltage regulator or does each rail need its own separate voltage regulator? Same with the VCCA_AXA0_1P2 and VCCA_AXA1_1P2, and for the VCCA_AXA0_0P9 and VCCA_AXA1_0P9." Any insight or experience tying these rails together you can share will be helpful. Thank youCyclone IV E Device VCCIO bank Power Supply related
Hi Team, We are using a Cyclone IV E (EP4CE30) device in our current design. In one of Altera’s application documents (AN 447), it is mentioned that: When LVTTL/LVCMOS signals are connected to an FPGA bank powered at 3.3 V VCCIO, series termination should be applied on the nets. It is also stated that if we want to connect these LVTTL/LVCMOS nets without any series termination, we can power the FPGA bank with 3.0 V VCCIO instead. please refer the below AN447 application note snippet (https://www.intel.com/programmable/technical-pdfs/683295.pdf) My questions are: Is this approach correct? Can 3.3 V LVTTL/LVCMOS signals be safely interfaced to an FPGA I/O bank powered at 3.0 V without violating input tolerance or causing long‑term reliability issues? What about FPGA outputs? If the FPGA bank is powered at 3.0 V VCCIO, and the FPGA drives LVTTL/LVCMOS outputs to external circuitry that expects 3.3 V levels, will this work reliably? Are the VOL/VOH levels still compliant? Are there any risks of reduced noise margin? In summary: Is powering the bank at 3.0 V a valid method to avoid adding series termination? What are the recommended practices for LVTTL/LVCMOS signaling in Cyclone IV E when the external system uses 3.3 V levels? Any clarification from Intel or others with experience using Cyclone IV E in such configurations would be greatly appreciated.
MAX10 ADC_VREF (Single Supply Device)
I am using a MAX 10 10M08SAE144C8G device (single-supply with internal ADC). Power setup: VCCIO banks: mostly 3.3 V, one bank at 2.5 V (per datasheet, mixed voltages allowed) VCCA: 3.3 V (per datasheet: “Connect these pins to a 3.0 V or 3.3 V power supplies…”) ADC_VREF was initially wired directly to the 3.3 V rail Observed behavior: With ADC_VREF tied to 3.3 V, the 3.3 V rail drew an additional ~200 mA Measuring ADC_VREF to GND (unpowered) showed approximately 20 Ω, which seems abnormal After isolating ADC_VREF from the 3.3 V rail, the excessive current draw on 3.3 V disappeared I have seen the same issue on all 4 prototype boards I've ordered. I can confirm the 200mA current is all going into the ADC_VREF pin but cannot explain why! Questions: Is ADC_VREF not intended to be tied directly to a low-impedance 3.3 V supply, even when VCCA = 3.3 V? Does ADC_VREF require a separate reference source (internal reference, precision external reference, or current-limited/filtered supply)? Does the low resistance (~20 Ω to GND) indicate likely permanent damage to the ADC reference circuitry? Are there recommended protection components (series resistor, RC filter, etc.) when using an external reference? I am using the ADC pins as digital pins driving some I2C busses, which are pulled up to 3.3V via 4k7 resistors according to the I2C spec. And here is my power supply sheet. All +3V3 supplies are derived from the same regulator - they are just filtered version (using LC filter) of the main regulator output. I’d appreciate clarification on the correct electrical usage of ADC_VREF and whether tying it directly to 3.3 V can cause latch-up or damage, even though VCCA itself supports 3.3 V. Thank you! LA
