Signal Tap Logic Analyzer II Trigger Condition
Hi i am working with DE1-SoC Cyclone V SoC FPGA Board and i am using quartus Prime Lite Edition. I am trying to use Signal Tap Logic Analyzer II but somehow i am not able to configure it correctly my trigger condition get triggered successfully but the data log in the logic analyzer is just the last value rather than all the previous values occur before trigger condition. What can be possible thing i am missing. Any guide on this topic will be very helpful. thanks in advancePlatform designer very slow when opening top level system (21.1 Std)
Hello, I am currently working on a FPGA project with the Quartus Prime Standard 21.1 software. When opening the top level QSYS-file it takes forever to finally finish (multiple hours). I have tested it with the same design on multiple machines including: - i7 8700K with 32GB RAM and corporate Windows 10 OS - i9 12900K with 64 GB and corporate Windows 10 OS - i5 7500 with 8 GB RAM and standard Windows 10 OS (to make sure it wasn't the corporate Windows 10 OS) The different hardware didn't seem to make a difference when opening the top level. When opening a subsystem that is instantiated in the top level the Platform Designer doesn't take nearly as long. All of them open within 1 minute and one -taht includes most of the logic - takes about 20minutes to open. When building the whole FPGA it takes 5.5h on the i7 8700K and 3h on the i9 12900K machine. Most of the time is spent in Analysis&Synthesis: the i7 takes about 4h and the i9 2.5h here. I assume that this is caused by the same problem that causes the top level file to be opened so slowly. I have worked on multiple designs with this version of Quartus but have never encountered a similar issue. The project I am currently working on consumes ~80% of the ALM and ~35% of the memory bits in the Arria 10 GX with 270kLE. Unfortunately I cannot share the files themselves due to corporate regulations. Are there any known issues with certain system design choices that can cause the platform designer/quartus to perform so poorly when opening or processing Analysis&Synthesis? Best Regards, Florianquartus system console font too small, windows 11, monitors 2496 / 1664
What is up with Quartus , using lates, on W11 , see in screen shot atatched, the text in the background, is a web browser, quiet happy with windows resolution, font is very readable, whilst Quartus , seems to be hard fixed for a resolution of around 1920 by 1220 Is there a setting one has to fiddle with to make the console readable ? or do I have to drop back 20 to a lower resolution monitor ?
NIOS ii/e clock frequency differ from real-time running frequency.
I have created a Qsys circuit using Nios II/e, with a clock frequency of 50 MHz. Other peripherals are also connected, as shown in the attached photo. I wrote a program in Eclipse, and when I checked the real-time toggling of the GPIO pin, I found the ON time to be 85 microseconds and the OFF time to be 86 microseconds. However, I specified an ON time and OFF time of 1 microsecond each in the program. Could you kindly help me understand why there is such a significant difference?
Nios-II/Nios-V future on Intel FPGAs
Hello, My colleagues and I teach a university course on FPGAs, and I have a question regarding the anticipated support for the Nios-V processor in Quartus. Until now, we have incorporated the Nios-II processor in Quartus Lite Edition for our coursework. However, we recently encountered a warning indicating that Nios-II is no longer recommended for new designs and that Nios-V should be considered as its successor. In light of this, I would like to know the future trajectory of Nios soft processors within Quartus Lite Edition. Should we continue to utilize Nios-II despite the warning, or are there any plans to integrate Nios-V support into the Lite Edition as well? I attempted to create an example Nios-V design, but it appears that the software flow is not supported in the Lite version. Given that Xilinx/AMD FPGAs offer the free MicroBlaze as a softcore processor, it would be disappointing if there were no long-term solution for Intel FPGAs. Thank you for your attention to this matter. Best regards, Jan
JTAG connection Issues with Intel FPGA Development Environment
Hello, I am currently encountering some issues with my Intel FPGA development environment and would appreciate assistance. I am using Quartus Prime Pro version 18.1.2.277, and the device in use is the Stratix 10 TX 1ST280EY2F55E1VG. USB-Ballaster II is detected, but the device shows 'Unable to connect.' Additionally, when attempting to run the board test system, the error message 'Fail to register GUI application!' appears, preventing the execution. Despite trying to lower the JTAG clock as instructed, the connection issue persists. Thank you for your assistance.
Problem with Quartus prim standard 24.1: I cannot generate IP for the hardware memory controller of
I am currently developing Cyclone VGX (5CGXFC7D7F27C8N). I am using Quartus prim standard 24.1. I purchased a board with LPDDR2-SDRAM mounted as external memory for 5CGXFC7D7F27C8N. I am trying to set the hardware memory controller and generate the IP, but an error occurs midway and the generation is not performed correctly. The script displays a message that the Nios II environment is required. The Nios II environment is not included in 24.1 and later. Do I have to downgrade to Quartus prim standard 23.1.1, which includes the Nios II environment?
LPM DIVIDE behaves differently between simulation and implementation
I have implemented a divider in a custom VHDL module in order to replace the instances of the LPM_DIVIDE IPs in my project. I've then checked the functionality of my module against the LPM_DIVIDE and verified through a simulation that, with the exception of a different initial latency, my divider behaves exactly the same way of the LPM_DIVIDE IP, covering all the dynamic of the input operands. The problem is that when I test it on the hardware, I have some slightly different results. Debugging the problem with SignalTap, I verified that the problem was due to a different behavior of the LPM_DIVIDE IP on the hardware with respect to the simulation. I verified that the different behavior occurs when the result of the division has a negative sign. I have attached the results of the simulation and of the acquisition on SignalTap in case of a division between a negative numerator and a positive denominator. The correct result should be the one of the simulation (0xFF..FFF4FF), but for a reason that I still don't understand, in the hardware implementation the result is 0xFF..FFF4FE. Do you have any suggestion? Is there some kind of rounding in the implementation that is not present in the simulation model?
