QSYS 25.3pro failed to generate VHDL simulation files for altera_remote_update_core
Hello, If I use altera_remote_update_core in a QSYS project using Quartus Version 25.3pro, the IP Generation fails with the following error message Info: sib_flash_subsys_remote_update_0: "Generating: altera_remote_update_core" Error: invalid command name "else" Info: while executing Info: "else { Info: do_vhdl_sim_cbx altera_remote_update_core Info: }" Info: (procedure "do_vhdl_sim" line 8) Info: invoked from within Info: "do_vhdl_sim altera_remote_update_core" Error: Generation stopped, 1 or more modules remaining Despite the error message being not very meaningful, I realized, that this fails only, when I select Simulation Model "VHDL". If I select simulation model "none" or "verilog" IP Generation works fine. The error is reproduceable by a simple QSYS project, which only contains altera_remote_update IP core. The error only occurs in Quartus 25.3pro. Using the exactly same project with Quartus 24.1pro works without error. Please advice, I would appreciate any help on this topic. Thanks best regards Fabian
Problem with wire level expressions in platform designer quartus pro 25.1
I have a platform designer system which uses wire level expression original produced using quartus pro 20.4. For a new project I am using this system with quartus 25.1. When opening the system platform designer reports that any component with a wire level expression endpoint is out of date. Upgrading the component does not resolve the issue, the only way to fix the issue is to remove the wire level expressions. Has wire level expression support changed in newer quartus versions and is there a way to work around this? Kind regards Graeme
How-to generate dual-port (read/write) RAM with clock enables
Following Stratix® 10 Embedded Memory User Guide (2025.07.24) chapter 2.11.6 independent clock enables are supported for read/write clock mode input/output clock mode I start a "RAM 2-port" IP generation. I select "one read/write port" in the general tab and "dual clock use separate read and write clock" in the "Clks/Rd,Byte En" tab. Now I enable the clock enables in the "Reg/Clkens/Aclrs" tab "use clock for read input register" as well as same for "output registers". IP Parameter window immediuately shows an error: Error: testram.ram_2port_0: Clock enable for read input registers is unavailable while using 'Dual clock: use separate read and write clocks' for Stratix 10 device family. This is verified with Quartus Pro 18.1 and 25.3. Is this a bug of the software or the documentation?
USB blaster not detected in Quartus 24.1
Hi, Recently updated from windows 10 to windows 11. Previously was using Quartus 19.1 and after upgrade USB blaster driver got corrupted. Below are the steps I did to debug the issue: Update driver via enforce driver disable in windows. Load usb blaster driver of quartus 24.1 Uninstall quartus 19.1 and USB blaster drivers. Installed Quartus 24.1 and USB blaster driver that came with it. Even after step 3, same issue. How can I solve it? Even though Quartus 24.1 USB blaster is supported in windows 11. Device Manager Error reporting when USB blaster is connected. Signal Tap doesn't recognize any hardware connected.
The correct way to install QUARTUS on UBUNUT 24.04 LTS?
Greetings QUARTUS experts, I have been trying (and failing!) to install QUARTUS Prime Pro on my UBUNUT 24.04 LTS LINUX machine. The QUARTUS documentation says that UBUNTU 24.04 LTS is a supported OS, so all should work fine ! Or Not ! After i have downloaded the installer, added the correct execute permissions, i run it and it appears to install everything. But the first problem i noticed is that it only takes a few seconds to run and then stops saying everything is installed. In comparison on my Windows 10 machine the installation process takes a couple of hours ! The next problem on Linux is that no QUARTUS Icons have been created in the UBUNTU applications area. And then when i try to run QUARTUS from the command line i just get a message saying of course it doesn't know where the heck Quartus is :) As expected really.... My question is then: What are the exact steps i need to take to get Quartus PRIME PRO to install correctly on my LINUX machine ? I do the usual steps before running the installer: $ sudo update & sudo upgrade etc.... Thanks for your help, Dr Barry Hdut.p0_hip_status has no associated reset.
Hello Altera I am using Quartus Prime Pro 25.1.0 build 129 03/26/2025 SC Pro Edition. In my Agiliex 7 Design project, I have Intel R-Tile MCDMA for PCI Express intel_pcie_rtile_mcdma Version 5.3.1 Ip instantiated as "dut". in parameters settings I have enabled to have hip status interface. this interface is connected to a custom design QCP file. The QCP uses "app_clk" and "app_nreset_status" from dut ip as its clk and reset inputs. THey go through clock bridge and reset bridge. Clock and reser outputs from these bridges are used internally in QCP creation In platform designer as I connect "dut.p0_hip_status" and "custom_module_pcie_ep_hip_status_in" I get an error as following "Error: pcie_ed: Interfaces custom_module_pcie_ep_hip_status_in and dut.p0_hip_status must have matching associated resets, but dut.p0_hip_status has no associated reset." This Error does not make sense to me, as dut`s hip status interface and my qcp`s status interface ports shows correct clock and reset association in component instantiation tab; and my custom design uses same clock and reset to its clock and reset bridge inputs. can you please help me to understand what is this error about and how do i resolve it?How to upgrade IP from Quartus 24.1 and add it to a Quartus 25.1 Project?
Hello ALTERA Quarts Experts, I have created and configured an ALT_PLL IP in Quartus Standard edition 24.1. Now i need to add that IP to a Quartus 25.1 Standard Edition project. I have tried this so far: added the IPs output files to my 25.1 project: readout_pll.qip, readout_pll.v, readout_pll_bb.v There is also a file called: readout_pll.ppf which appears to be an xml file. Not exactly sure what this is meant to do or if i also needed to add that? I then see the message from Quartus 25.1 asking me to do an auto IP upgrade, which id did and it was successful according to Quartus. But then i don't see the IP appear in the projects IP Catalogue even after i do an IP library refresh. Can anybody please tell me what else i need to do in order to be able to use the IP in my 25.1 Project ? I am having to do all this because the ALT_PLL symbol is all messed up and is unusable in Quartus Standard Edition 25.1. For That problem i have already created another post recently and have been assured this will be fixed. But for now until its fixed i need to do this IP upgrade. Thanks, Barry
The FIFO has no output waveform
Hi, I am currently using Quartus Prime Lite 24.1 and the 10M02M153C8G device to implement an 8Kx9 SYNC FIFO. I generated the design directly using the IP CORE. Initially, my tests successfully produced output waveforms. However, I must have changed a setting unintentionally, as I am now unable to simulate the output. Even previous projects that worked before are no longer producing any waveforms. I subsequently observed the following messages in the Simulation flow progress: Warning: sclr - signal not found in VCD. Warning: wrreq - signal not found in VCD. These warnings are appearing for multiple signals, as shown in the image or attachment (referring to the image/attachment). I have already tried reinstalling the software and updating the license options, but the issue persists. Could you please advise on the cause of this problem and how to resolve it? Thank you for your assistance.
