PCIe configuration/capability list
Hi, So we've been testing a custom hardware card connected to a server with Ice Lake CPUs, and found it's been disconnecting over the PCIe connection. This is compared to an identical configuration but with Cascade Lake CPUs, where it managed to work. This was done using CentOS 8 Stream. I was wondering if there've been any changes to the PCIe capabilities, or anything else relevant that could help explain this. I'll also include an error message that might help, on sending a command to the hardware that causes it to fail: Hardware error from APEI Generic Hardware Error Source: 5 event severity: recoverable Error 0, type: fatal section_type: PCIe error port_type: 4, root port version: 3.0 command: 0x0547, status: 0x4010 device_id: 0000:b0:04.0 slot: 4 secondary_bus: 0xb1 vendor_id: 0x8086, device_id: 0x347c class_code: 000406 bridge: secondary_status: 0x2000, control: 0x0003 aer_uncor_status: 0x00004000, aer_uncor_mask: 0x01310000 aer_uncor_severity: 0x044ef030 TLP Header: 00000001 fc22fe01 dbc04000 00000000 Thanks, Matthew
How can I port RTL module into oneAPI FPGA programming ?
Hi there, I have been using oneAPI for FPGA programming for a while. I am now trying to port my well-defined RTL module into my oneAPI implementation. I do read and understand the specification documents provided in oneAPI websites also the openCL SDK development. However, one of these have pointed a very clear way to interact with RTL module using oneAPI. I am successfully runing a combinational vector-add sample myself, but have no idea how to interact with the sythesized modules from oneAPI with clock driven capability and Avalon-ST interface. Have anyone done such a tryout before ? Best.
IFFT
Dear sir, I encountered the following problems when using FFT IP core to simulate My FFT IP core configuration is as follows.I configure it as IFFT. In the case of entering the same data, Sometimes, I can get the right results, as shown in the following figure: But sometimes, I always get wrong results, as shown in the following figure: What may be the cause of this abnormal output? We are looking forward to your reply.Cannot send information to education registration support
Re: Information Required: Intel® FPGA Academic Program Membership Application L-013561 ref : 00Q7V00001wsNV2UAM Joseph Gabbay <josephg@mail.afeka.ac.il> 8:42 AM (9 minutes ago) to FPGA Hello I am trying to answer but the email bounces back. Here is another trial, let's hope this time it is OK, Is this link good enough? Joseph Gabbay | Afeka College - higher engineering studies in Tel Aviv Attached pictures: the first is taken from the WWW (you have a link), The other is taken from Afeka's intranet system (may be limited to staff members as it requires authentication) It is written in Hebrew, you can still verify my phone number as well... Thank you Regards, Joseph Gabbay
The design is right, but the execution is wrong
Good evening and Happy New Year everyone.. Implemented this equation: Attached is a picture with the file Bit depth: from 8 to 28 Algorithm type: The process of multiplying the highest digits of the multiplier begins with a fixed sum of the partial product and shifts the multiplier to the right by one digit per turn. The multiplier shifts to the left This build is on Quartus II 9.1sp2 Web Edition But when executing, the error appears Error: Illegal name "A[27]" -- pin name already exists Error: Illegal name "A[27]" -- pin name already exists Error: Illegal name "A[27]" -- pin name already exists Error: Can't elaborate top-level user hierarchy Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 1 warning Error: Peak virtual memory: 235 megabytes Error: Processing ended: Sun Jan 01 19:56:31 2023 Error: Elapsed time: 00:00:00 Error: Total CPU time (on all processors): 00:00:01 Error: Quartus II Full Compilation was unsuccessful. 6 errors, 1 warning
Timing for Quartus Multiply .BDF module
I am using a large number of Quartus IP LPMMULT "Basic Functions" both in parallel and then in series to calculate a 32 bit number from a large number of 16 bit (unsigned) array of numbers. Its a large branched tree. I assume each multiplication takes place with a low to high clock pulse. How do I know when the calculation is done to issue a clock pulse to the next adder using a pair of result[31..0] values from the previous multiplier. ---->Mult---->Mult---->Mult | ---->Mult--->Mult---- | ---->Mul---> Any help here from an expert would be appreciated -- I'm new to Quartus. PS this may be the wrong location for this question, if so where is best.
