413 Results
Why are there PCIe* functional failures observed after a Configuration via Protocol (CvP) update in Agilex® 7 FPGA devices (R-Tile) CvP designs?
Description Due to a problem in Quartus® Prime Pro Edition software versions 25.3.1 and earlier, when using Configuration via Protocol (CvP) for Agilex® 7 FPGA devices (R-Tile), you may observe PCIe...88Views0likes0CommentsHow is ACKNAK_LATENCY_TIMER defined in PCIe base spec work inside PCIe core ?
Description ACKNAK_LATENCY_TIMER is used as a priority mechanism so that when there is a long stream of back-to-back transmit traffic ACKs can be inserted into the transmit stream to prevent the c...299Views0likes0CommentsIntel® Arria® 10 FPGA PCIe 3.0 Endpoint is not compatible with PCIe 4.0 capable system.
Description The Intel® Arria® 10 FPGA PCIe 3.0 IP core will treat 4.0 Data Link Features Exchange as unsupported DLLP type (as per the PCIe 3.0 spec), unsupported DLLP type is not being f...207Views0likes0CommentsWhy can't I enable Virtual Functions on a PCIe endpoint implemented with the GTS AXI Streaming IP for PCI Express*?
...RI) feature is not enabled in the host system's BIOS, even when the device implements fewer than eight functions. While ARI is typically required only for PCIe endpoints with more than eight functions, t...60Views0likes0CommentsWhy are GTS transceiver tests including PCIe* enumeration failing on the Agilex™ 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1)?
...SPI flash. This corrupt image results in failures in transceiver operation even if a new image is loaded via JTAG. Examples of issues include failure of the PCIe* to enumerate and SFP t...86Views0likes0CommentsWhy does the BAM (Bursting Avalon‑MM Master) module of the GTS AXI Multichannel DMA IP for PCI Express* fail to generate Completion TLPs in a PCIe Root Port implementation?
Description Due to a problem in Quartus® Prime Pro Edition software version 26.1, the BAM in the AXI Multichannel DMA IP for PCI Express* may fail to return Completion TLPs in simulation once the c...13Views0likes0CommentsWhy does the PCIe link not come up, when I first plug in the Arria™ GX PCIe development kit board into a PCIe slot?
Description In some Arria GX PCIe development kits (production release), the factory pre-installed programming file (.pof) may not be the one for running the PCIe high performance reference design....97Views0likes0CommentsWhy does the PCIe* link remain at the Polling.Compliance state after reconfiguring the Agilex™ 5 FPGA E-Series 065B Development Kit?
...nused. The presence of the termination at the upper four unused lanes can lead to complications at the root port during reconfiguration. You might notice that the PCIe* link becomes stuck in the P...118Views0likes0Comments
