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Why are there PCIe* functional failures observed after a Configuration via Protocol (CvP) update in Agilex® 7 FPGA devices (R-Tile) CvP designs?
Description Due to a problem in Quartus® Prime Pro Edition software versions 25.3.1 and earlier, when using Configuration via Protocol (CvP) for Agilex® 7 FPGA devices (R-Tile), you may observe PCIe...247Views0likes0CommentsHow is ACKNAK_LATENCY_TIMER defined in PCIe base spec work inside PCIe core ?
Description ACKNAK_LATENCY_TIMER is used as a priority mechanism so that when there is a long stream of back-to-back transmit traffic ACKs can be inserted into the transmit stream to prevent the c...407Views0likes0CommentsIntel® Arria® 10 FPGA PCIe 3.0 Endpoint is not compatible with PCIe 4.0 capable system.
Description The Intel® Arria® 10 FPGA PCIe 3.0 IP core will treat 4.0 Data Link Features Exchange as unsupported DLLP type (as per the PCIe 3.0 spec), unsupported DLLP type is not being f...356Views0likes0CommentsWhy are GTS transceiver tests including PCIe* enumeration failing on the Agilex™ 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1)?
...SPI flash. This corrupt image results in failures in transceiver operation even if a new image is loaded via JTAG. Examples of issues include failure of the PCIe* to enumerate and SFP t...282Views0likes0CommentsDoes the Agilex® 7 FPGA F-Series (2 × F-Tiles) Development Kit support CvP over the PCIe* 4.0x16 Gold Fingers?
Description The Agilex® 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023) do not support CvP over the PCIe* 4.0x16 Gold Finger Card Edge connector. CvP is supported over the MCIO x4 interface....47Views0likes0CommentsWhy can't I enable Virtual Functions on a PCIe endpoint implemented with the GTS AXI Streaming IP for PCI Express*?
...RI) feature is not enabled in the host system's BIOS, even when the device implements fewer than eight functions. While ARI is typically required only for PCIe endpoints with more than eight functions, t...110Views0likes0CommentsWhy do I get an Internal error message when compiling my PCIe design that was migrated from previous Quartus II software version with different PCIe link width?
Description This is due to the inconsistent settings between the IP compiler for PCI® Express and the ALTGX, such as the IP compiler for PCI Express being set to x4 lanes, however in the ALTGX it d...273Views0likes0Comments
