Knowledge Base Article
Why are there PCIe* functional failures observed after a Configuration via Protocol (CvP) update in Agilex® 7 FPGA devices (R-Tile) CvP designs?
Description
Due to a problem in Quartus® Prime Pro Edition software versions 25.3.1 and earlier, when using Configuration via Protocol (CvP) for Agilex® 7 FPGA devices (R-Tile), you may observe PCIe* functional failures after performing a CvP update, as the PCIe interface becomes non-functional.
During the CvP update, the FPGA fabric is reconfigured and held in reset, while the PCIe Hard IP is not reset. This issue occurs because the R-Tile RTL is unable to handle the handshaking between the PCIe Hard IP and the fabric after the CvP update. Note that this issue does not cause the PCIe link to go down.
This issue affects designs using R-Tile with both CvP and PCIe. Designs using R-Tile without CvP are not affected.
This issue occurs in the following flow:
- CvP Periphery image
- CvP Initialization
- CvP Update
- PCIe activity
- Issue observed
The following sequences will not trigger the problem:
- A CvP update without PCIe activity after CvP Initialization
- PCIe activity without a CvP Update after CvP Initialization
Resolution
To work around this problem, reconfigure the FPGA.
Note that this fix may introduce a few seconds of additional delay during the CvP update in the teardown process. This delay occurs after the core.rbf file is transferred during every CvP update. During teardown, the CvP driver polls the CVP_CONFIG_READY bit in the CvP Status Register until CVP_CONFIG_READY equals 0, which accounts for the additional delay.
This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.
Related IP
- R-Tile Avalon Streaming IP for PCI Express
- Multi Channel DMA IP for PCI Express
- AXI Streaming IP for PCI Express