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Honored Contributor
Honored ContributorDE2 Lab 4, Part 4 (VHDL) - Digital Logic
I'm new to VHDL and FPGAs but need to learn how to program with it for my graduate studies. I decided to try out the tutorials and labs on Altera's web site to get a start and have managed to work my way up to this lab. (Btw, if anyone has any other tutorials, books you'd recommend to a beginner, I'd love to hear about them).
Anyway, I got up to Lab 4, Part 4. In order to get it to work I've used a 26-bit counter from the megafunctions library. 50 000 000 clock cycles (10111110101111000010000000 in binary) from the CLOCK_50 MHz signal corresponds to 1 sec of course. After the counter reaches this point through value Count, I increment the Num signal and assert the Clear signal in the counter, otherwise the Clear signal remains off. I also have an if statement to keep the Num within 0-9 on the 7-segment display. My logic can be seen in the top level code below.LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY part4 IS
PORT ( HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLOCK_50 : IN STD_LOGIC);
END part4;
ARCHITECTURE Behavior OF part4 IS
COMPONENT num_7seg
PORT ( M : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Display : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END COMPONENT;
COMPONENT megacounter
PORT (aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
cnt_en : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (25 DOWNTO 0));
END COMPONENT;
SIGNAL Count : STD_LOGIC_VECTOR(25 DOWNTO 0);
SIGNAL Num : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Clear : STD_LOGIC;
BEGIN
A0: megacounter PORT MAP (Clear, CLOCK_50, '1', Count);
PROCESS (Count)
BEGIN
IF (Count = "10111110101111000010000000") THEN
Num <= Num + '1';
Clear <= '1';
IF (Num > "1001") THEN
Num <= "0000";
END IF;
ELSE
Clear <= '0';
END IF;
END PROCESS;
D0: num_7seg PORT MAP (Num,HEX0);
END Behavior;
