DE2 Lab 4, Part 4 (VHDL) - Digital Logic

Thanks for the advice guys. It helped steer me in the right direction.

I got rid of the megafunction counter and created my own. I also got rid of the clear signal and just decided to reset the counter manually.

This ended up working:

   PROCESS (CLOCK_50)
   BEGIN
      IF rising_edge(CLOCK_50) THEN
         Count <= Count + '1';
         IF (Count = "10111110101111000010000000") THEN
            Num <= Num + '1';
            Count <= "00000000000000000000000000";
            IF (Num = "1001") THEN
               Num <= "0000";
            END IF;
         END IF; 
      END IF;
   END PROCESS;
      
   D0: num_7seg PORT MAP (Num,HEX0);

In regards to the packages and types that I use, those are the ones they discuss and use in the tutorial/lab exercises on the Altera webiste as well as the digital logic textbook by Brown & Vranesic that Altera recommends. I'll take your advice however. Thanks again.