Arria10 Transceiver Oversampling

Dear Community,

I am trying to set up the MGTs of my Arria 10 GX (10AX115N2F45E1SG) FPGA to send data at a rate of 125 Mbps. This should be the lowest possible rate according to table 3 of the Arria 10 Device Overview. I also found the demo design no. 19 "Arria10 GX SI Board : 11x Oversampling Design using 4 lanes at 150 Mbps using PRBS". Unfortunately, from the slides included in that demo design, I am not sure how to set up my own transceiver. However, I used it as orientation.

I set up the respective IP core "Transceiver Native PHY" as TX Simplex with two data channels running at a rate of 1250 Mbps in the standard PCS configuration with an interface width of 10.
The fPLL receives a 125 MHz reference clock from an oscillator and creates from that a 625 MHz clock.
I use the "tx_clkout" port from the transceiver to clock my own data generator. It has a frequency of 125 MHz. This output is connected to "tx_coreclkin" input.

With these settings, the data has a rate of 1250 Mbps, which does not surprise me but leaves me wondering how to achieve the 10x Oversampling?

I also tried to clock my data generator with a 12.5 MHz clock, which I created by using an IOPLL that receives its reference from tx_clkout. So I connected the tx_coreclkin port to the 12.5 MHz clock. But again the observed data rate was 1250 Mbps and not the desired 125 Mbps.

I hope someone of you can help me. Thank you!