DE2 Lab 4, Part 4 (VHDL) - Digital Logic

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I'm not sure how this would synthesize, but you should make your process clocked instead of depending on the counter. What you are describing here is to keep on increasing num as long as the count vector is at that value, not just increase it once when you reach the value. This code will probably generate a combinatorial loop that will give unpredictable results.

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Oh yeah, I forgot compiler ignores sensitivity.

This highlights another issue - simulation/synthesis mismatch. The code that was origionally written would probably synthesise to the infinite counter Daixiwen mentioned, but in simulation it would look like a transparent latch.