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Altera_Forum
Honored Contributor
Honored ContributorDE2 Lab 4, Part 4 (VHDL) - Digital Logic
I'm new to VHDL and FPGAs but need to learn how to program with it for my graduate studies. I decided to try out the tutorials and labs on Altera's web site to get a start and have managed to work my...
Altera_ForumHonored Contributor
Honored ContributorOh yes now that I read again what I wrote, I realise I wasn't entirely clear in my explanation. ;)
In pure theory (and in simulation) the original code should work because the process is supposed to be only triggered when 'count' changes, and it will do a latch. In practise though, the synthesizer ignores the process sensitivity list and that's why we'll have the infinite loop.
