DE2 Lab 4, Part 4 (VHDL) - Digital Logic

There will be a problem having your process sensitive to count rather than making it synchronous. With your asynchronous design, what you're asking it to do is create a transparent latch that latches the value of num when the count is equal to that silly long binary number. My solutions:

1. make the proces synchronous to clk, not count, and follow the standard synchronous process template:

process(clk)
begin
     if rising_edge(clk) then
         --do some logic
     end if;
end process;

2. As you're a beginner, please stop using std_logic_unsigned/signed/arith now. They are not standard packages. They were written origionally by synopsys to make some things easier. Since then (in 1993!) the IEEE standardised the numeric_std package. It meant that this package was standard rather than having different versions created by different vendors, plus you can do signed/unsigned arithmatic in the same file (not possible with std_logic_vectors) and you can do division.

3. VHDL is strongly typed. It is much better to use appropriate types. a std_logic_vector is NOT a number, it is a collection of bits. Use integer/natural/positive if you actually mean integer, and unsigned/signed types (from the numeric_std package) if you want a binary version of numbers. so instead of

if count = "110101001001001010" then...

you can write instead:

if count = 150000 then

or if you prefer hex literals:

if count = 16#AAAA# then ..

This also carries for port maps. It is an old thing that old synthesisors insisted that ports had to be std_logic/std_logic_vector. Since then synthesisors support many many many different types - so you can quite happily use integer, boolen, signed/unsigned as ports on entities.

So, learn now that you can make your code more readable, with the compiler doing all the work. Good habits learned now are better than bad habits unlearned later.