DE2 Lab 4, Part 4 (VHDL) - Digital Logic

I'm not sure how this would synthesize, but you should make your process clocked instead of depending on the counter. What you are describing here is to keep on increasing num as long as the count vector is at that value, not just increase it once when you reach the value. This code will probably generate a combinatorial loop that will give unpredictable results.

So the first rule is to make your process dependent on the clock only:

    PROCESS (CLOCK_50)

And then in the process, only accomplish what you want on the rising edge of the clock

   BEGIN
      IF rising_edge(CLOCK_50) THEN 
         IF (Count = "10111110101111000010000000") THEN
            Num <= Num + '1';
            Clear <= '1';
            IF (Num > "1001") THEN
               Num <= "0000";
            END IF;
         ELSE
            Clear <= '0';
         END IF;       
      END IF;
   END PROCESS;  

Please note that doing it that way will add one cycle latency between the counter and your process. The value you will see in the 'Count' variable will be the counter output from the previous clock cycle. You may need to subtract one to your maximum counter value to have the exact number of cycles.

I would also recommend to forget about ieee.std_logic_unsigned.all and use ieee.numeric_std and the unsigned/signed types instead.