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Altera_Forum
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15 years ago

DE2 Lab 4, Part 4 (VHDL) - Digital Logic

I'm new to VHDL and FPGAs but need to learn how to program with it for my graduate studies. I decided to try out the tutorials and labs on Altera's web site to get a start and have managed to work my...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

It is unfortunate that tutorials and books on the web still refer to those non standard and confusing libraries... But as Tricky said, it's better to try and get the good habits as soon as possible ;)

Just a remark on your code. As you may have noticed, the signals aren't updated immediately in a process. This is because of the hardware that is generated. Every statement inside the clocked part of the process read the value of the signal at the clock rising edge and assignments give the value that they must take after that.

So in those lines:
Count <= Count + '1';
         IF (Count = "10111110101111000010000000") THEN
inside the if, the value that you see for 'Count' is still the old value, not the one added by 1. Therefore I think that you are counting one value too far. Don't think it is very noticeable, but as an exercise, it's better to have it right ;)