Forum Discussion
New ContributorStratix 10 Linux SD card booting
New ContributorHi Hector,
Yes, virtually they should be the same.
I boot the SD card from the Rocket board, and then I insert it into the FPGA, while I am doing minicom, I got this error. u-boot.img error - - 2
I have a question, do I need to flash the FPGA with the .jic file of a particular board (Suppose it can be SX, DX, TX, AX, whatever)? What if I compiled the GSRD design successfully, got the sof file, changed to the rbf file, and tried to boot it, and got an error like:
1. Do I need to program the MT25QU02G device with jic file, and then I reboot the FPGA (Minicom).
2. Just wondering what standard operating procedure is for Stratix 10 Board for HPS (Linux Booting).
Thank you.
New ContributorHi Bishnu ,
Sorry for the late response.
The Agilex 7 boot process is explained in great detail in the Agilex™ 7 SoC FPGA Boot User Guide. All the next information assumes that you are going to boot the HPS first and then you are going to configure the fabric as described here. Addressing your questions:
1. Do I need to program the MT25QU02G device with jic file, and then I reboot the FPGA (Minicom).
If you are trying to exercise the binaries yes, you need to load the JIC and flash the SD card with the provided image. See my next answer to know why you need both.
2. Just wondering what standard operating procedure is for Stratix 10 Board for HPS (Linux Booting).
The HPS boot process requires 2 parts to work:
- You need a First Stage Boot Loader (FSBL) start the HPS and configure a minimal set of peripherals an prepare the system to load an OS.
- The FSBL its embedded into the FPGA configuration file. You can use a JIC file (with the onboard QSPI) or you use an RBF file and load it with the Quartus programmer through JTAG. The following link has more information about this.
- A Second Stage Boot Loader (SSBL) brings-up the FPGA fabric and load an OS.
For our GSRDs the flow that we use is as follows:
- Compile the Quartus Hardware project
- Break the resulting SOF file into RBFs for the HPS only and Core only.
- Build the Yocto project including the Core RBF from the previous step
- Update the HPS configuration file with the FSBL generated with the Yocto compile and create a JIC file from it.
- Flash the SD card image generated by Yocto. This image includes the SSBL and the RBF to configure the FPGA fabric.
Then, to boot the system follow the next steps:
- Insert the SD card into the Development Kit
- Load the HPS bitstream (JIC file) into the devkit QSPI (MT25QU02G) and change the MSEL in the board to start from the QSPI or load the HPS bitstream with JTAG (this requires an RBF instead of a JIC file).
You need to take in consideration that you cannot mix SD cards and JIC files, or in other words FASBL and SSBL. For example, you cannot take the SD card generated for project A and use the JIC file from project B, this also holds true for different families, you cannot reuse a SD card from a SX device with a TX device.
To really understand the flow I recommend that you follow all the Rebuild the Binary section from the GSRD.
Regards
- HectorC_Altera
- Bishnu
Hi Hector,
https://docs.altera.com/r/docs/683838/20.3/an-923-routing-stratix-10-hps-peripherals-to-fpga-fabric/an-923-routing-stratix-10-hps-peripherals-to-fpga-fabric
I am doing it. I think now I understand the tool flow. I am wondering: is there any updated version for AN923? It has not been updated since 2020. Thank you.
