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New ContributorHow to access entire 4GB DDR from Agilex 7 HPS
We have a configuration where the Agilex 7 HPS EMIF interface is connected to 4GB DDR on the board. However the Linux/uboot is able to access only 2GB i.e address 0x0 - 0x7FFF_FFFF, while from F2H Acelite interface we can access the entire 4GB 0x0 - 0xFFFF_FFFF.
The Agilex™ 7 Hard Processor System Technical Reference Manual , does https://www.intel.com/content/www/us/en/support/programmable/articles/000090809.html But even after enabling that we aren't able to access the address 0x10_8000_0000 - 0x10_FFFF_FFFF neither from the uboot using "md" command nor from the acelite. The app note does refer to Stratix10 instead of Agilex7 , so not sure if its even relevant.
Any pointers on how to access the entire 4GB DDR from HPS in Agilex7.
9 Replies
chanderHi,
We made following changes to u-boot-socfpga/arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi
memory {
/* 4GB */
reg = <0 0x00000000 0 0x80000000>,
<0x10 0x80000000 0 0x80000000>;
};Apart from this we made the following change in u-boot-socfpga/arch/arm/mach-socfpga/spl_agilex7.c
writel(0x80000000, 0xF8020110); // region0addr_base
writel(0x10, 0xF8020114); // region0addr_baseext
writel(0xFFFFFFFF, 0xF8020118); // region0addr_limit (lower 32bits)
writel(0x10, 0xF802011C); //region0addr_limitext (upper 32bits)
writel(0x1, 0xF8020104); //enable_set for regions
writel(0x80000000, 0xF8020210); // region0addr_base
writel(0x10, 0xF8020214); // region0addr_baseext
writel(0xFFFFFFFF, 0xF8020218); // region0addr_limit (lower 32bits)
writel(0x10, 0xF802021C); //region0addr_limitext (upper 32bits)
writel(0x1, 0xF8020204); //enable_set for regions
writel(0x1, 0xF8020204); //enable_set for regionsBut in the uboot , the md 0x1080000000 1 , hangs
- chander
Hi Aik Eu,
Do we also need to make changes to the firewall_ddr_fpga2sdram_inst_0_scr registers?
Could you tell us the changes needed in u-boot-socfpga/arch/arm/mach-socfpga/spl_agilex7.c if any ? We are using AGMF039 device.regards
Chander
tehjingy_AlteraRegular Contributor
Hi
Any update on this case?
Did the changes suggested on the device tree solved your issue?
Regards
Jingyang, Teh
- tehjingy_Altera
Hi
Once you have added the DDR correctly in the device tree and managed to detect the DDR.
You are able to access the DDR from address space 0x00 to 0x00_7FFF_FFFF (2GB) and 0x01_0000_0000 to 0x1F_FFFF_FFFF ( remaining DDR)
As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Regards
Jingyang, Teh
Ashish-TrivediHi JingYengTeh,
no none of these changes worked.
diff --git a/arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi
index eb5c7c70..965f1b81 100644
--- a/arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi
@@ -31,7 +31,8 @@
/* 2GB */
/* reg = <0 0x00000000 0 0x80000000>; */
reg = <0 0x00000000 0 0x80000000>,
- <2 0x80000000 0 0x80000000>;
+ <0x10 0x80000000 0 0x80000000>;
+ /* <0x2 0x80000000 0 0x80000000>;*/
};
};We had tried all these below combinations
1. <0x10 0x80000000 0 0x80000000>;
2. <0x2 0x80000000 0 0x80000000>;3. <0x20 0x80000000 0 0x80000000>;
- chander
Hi Jingyang Teh,
Haven't heard back from you. Would a meeting help to resolve this quicker.
regards
Chander
