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chander's avatar
chander
Icon for New Contributor rankNew Contributor
2 years ago

How to access entire 4GB DDR from Agilex 7 HPS

We have a configuration where the Agilex 7 HPS EMIF interface is connected to 4GB DDR on the board. However the Linux/uboot is able to access only 2GB i.e address 0x0 - 0x7FFF_FFFF, while from F2H Ac...
Arm Processor
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi


Once you have added the DDR correctly in the device tree and managed to detect the DDR.

You are able to access the DDR from address space 0x00 to 0x00_7FFF_FFFF (2GB) and 0x01_0000_0000 to 0x1F_FFFF_FFFF ( remaining DDR)

https://www.intel.com/content/www/us/en/docs/programmable/683567/23-1/l3-address-space-falconmesa.html


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Regards

Jingyang, Teh


Ashish-Trivedi's avatar
Ashish-Trivedi
Icon for New Contributor rankNew Contributor
2 years ago

Hi JingYengTeh,

no none of these changes worked.

diff --git a/arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi
index eb5c7c70..965f1b81 100644
--- a/arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi
@@ -31,7 +31,8 @@
/* 2GB */
/* reg = <0 0x00000000 0 0x80000000>; */
reg = <0 0x00000000 0 0x80000000>,
- <2 0x80000000 0 0x80000000>;
+ <0x10 0x80000000 0 0x80000000>;
+ /* <0x2 0x80000000 0 0x80000000>;*/
};
};

We had tried all these below combinations

1. <0x10 0x80000000 0 0x80000000>;
2. <0x2 0x80000000 0 0x80000000>;

3. <0x20 0x80000000 0 0x80000000>;