New Contributor
Regular ContributorHi chander,
May I know how is the device tree being defined in your system?
Example below if for Agilex dev kit 8GB
memory {
/* 8GB */
reg = <0 0x00000000 0 0x80000000>,
<2 0x80000000 1 0x80000000>;
};
Link from the content above:
Thanks.
Regards,
Aik Eu
New ContributorHi,
We made following changes to u-boot-socfpga/arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi
memory {
/* 4GB */
reg = <0 0x00000000 0 0x80000000>,
<0x10 0x80000000 0 0x80000000>;
};
Apart from this we made the following change in u-boot-socfpga/arch/arm/mach-socfpga/spl_agilex7.c
writel(0x80000000, 0xF8020110); // region0addr_base
writel(0x10, 0xF8020114); // region0addr_baseext
writel(0xFFFFFFFF, 0xF8020118); // region0addr_limit (lower 32bits)
writel(0x10, 0xF802011C); //region0addr_limitext (upper 32bits)
writel(0x1, 0xF8020104); //enable_set for regions
writel(0x80000000, 0xF8020210); // region0addr_base
writel(0x10, 0xF8020214); // region0addr_baseext
writel(0xFFFFFFFF, 0xF8020218); // region0addr_limit (lower 32bits)
writel(0x10, 0xF802021C); //region0addr_limitext (upper 32bits)
writel(0x1, 0xF8020204); //enable_set for regions
writel(0x1, 0xF8020204); //enable_set for regions
But in the uboot , the md 0x1080000000 1 , hangs
