chanderNew Contributor1 year agoHow to access entire 4GB DDR from Agilex 7 HPS We have a configuration where the Agilex 7 HPS EMIF interface is connected to 4GB DDR on the board. However the Linux/uboot is able to access only 2GB i.e address 0x0 - 0x7FFF_FFFF, while from F2H Ac...Show More
aikeuRegular Contributor1 year agoHi chander,As I know only the device tree will need to be change.Thanks.Regards,Aik Eu
Recent DiscussionsArria 10 SoC – USB devices always enumerating as Full-Speed (Yocto 4.1, dwc2)Agilex5 - Bridge AXI F2H - read transactionsAgilex 5 Premium Dev Kit Ethernet PerformanceSupport Request to Debug Signal Tap Issue with SoC Based Design(GHRD) on Agilex-7 FPGARelease 25.3.1 PRO