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ohfpga1's avatar
ohfpga1
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12 days ago

Agilex5 - Bridge AXI F2H - read transactions

Hi, we are using in our design the bridge F2H between FPGA and HPS, which is a bus ACE5lite 256bits. Several masters AXI 64bits in our design will contact it via an interconnect.

In Write, no problem, we can attaquer this interface in « narrow transfers » 64b over 256b, in conformity with ARM specification.

But in READ, the SoC user manual (814346, 2026.01.09) says §11.5.1 :

« The HPS F2H interface has a fixed data size of 256-bits. This interface allows for narrow burst sizes less than 256-bits However, if a fabric initiator generates a transfer narrower than the interface width (i.e., less than the 256-bits wide data and a nonzero burst size), there is no guarantee that the HPS F2H interface will respond with narrower data aligned on non-256-bit boundaries of the 256-bit data bus. For example, if ARADDR = 0x0010_0000, ARSIZE = 0x4, and ARLEN = 0x3, the HPS F2H interface returns two beats of 32 bytes per beat followed by two null cycles, instead of four beats of 16 bytes per beat. Altera recommends that you add width adaptation interconnect logic between the fabric initiator and the HPS F2H interface to ensure that the narrow-width data is packed/unpacked properly.”

« the HPS F2H interface returns » : means it is sure that… , we will be able logic tranlation  256>64 considering that data returned on RDATA bus will fill all width of 256b (if enough read bytes of course).

If  “there is no guarantee…”  is correct, it is a problem as there is no Read Strobe with bus RDATA in AXI spécification ; and we can not determine which bytes of which BEATs of transfert have to be considered.

Last possible interpretation : the  ‘width adaptation interconnect logic’ recommanded by Altera concerns more the transformation of ARADDR/ARSIZE/ARLEN by our interconnect at bridge input (AR* parameters are requests of read sent by our masters should be translated by interconnect before to be presented to bridge).

Can you tell me the right meaning ?

Thanks and regards

 

1 Reply

  • KianHinT_altera's avatar
    KianHinT_altera
    Icon for Frequent Contributor rankFrequent Contributor
    11 hours ago

    Hi ohfpga1

    Apologies for the long delay in the response to your question. 

     

    From the HPS reference manual document for Agilex 5,  the recommendation is that width adaptation logic is required to handle 256-bit data packing and unpacking at the RDATA interface, not merely to translate ARADDR/ARSIZE/ARLEN parameters before presenting requests to the bridge. The F2H bridge returns data aligned to 256-bit boundaries (with potential null cycles for narrow requests) rather than true narrow beats, and requires AxSIZE to match the full 256-bit data bus width 

     

    in the documentation also mentions about the rw/wr data must be equal to the data bus width

     

    Therefore, the width adapter logic must intercept the 64-bit master's request and translate the ARADDR, ARSIZE (forcing it to 0x5 for 256-bit), and ARLEN before presenting it to the F2H bridge on the request part.

     

    As width adapter forced the bridge to perform a standard full-width 256-bit, the bridge will  in turn will return 256-bit aligned beats. The adapter must now act as a downsizer, capturing that 256-bit RDATA beat, unpacking it, and slicing it into the expected 64-bit beats with the correct valid/last signaling for the original master.

     

    In short the F2H bridge does not natively support standard AXI narrow reads thus width adaptation logic is needed to ensure the bridge is operating at 256bit (convert narrow AxSIZE request to 256bits) and to handle the unpacking of 256bit RDATA. 

     

    Hope it addresses your question on the AXI F2H.

     

    Thanks

    Regards

    Kian