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ohfpga1's avatar
ohfpga1
Icon for New Contributor rankNew Contributor
4 months ago

Agilex5 - Bridge AXI F2H - read transactions

Hi, we are using in our design the bridge F2H between FPGA and HPS, which is a bus ACE5lite 256bits. Several masters AXI 64bits in our design will contact it via an interconnect. In Write, no proble...
Hps Boot
KianHinT_altera's avatar
KianHinT_altera
Icon for Frequent Contributor rankFrequent Contributor
3 months ago

Hi,

As we did not hear back from you and the case been idling for some time, I will set this case to closure and transition to community support.
Thank you for engaging with us!

Best regards,
Kian