after pass payload to CRC generator, wireshark do not receive any ethernet frame i guess wrong, i do not know where to check, i am afraid that ethernet port in PC side drop the frame from FPGA when CRC is wrong any other methods to see whether it send or not no matter CRC is wrong or not? which data should be passed to CRC generators, whole ethernet frame? if so, does it include preamble?

What CRC generator are you talking about? If you are using the TSE, it included its own CRC generator. Just send the Ethernet frame without the preample nor CRC.

First I'd appreciate if you could simplify your code and removed all the commented out code lines, it would make it easier to read. Second you still aren't implementing your process right. I have no idea how Quartus will synthesize what you described, but it's probably not what you want. I suggest that you read this document (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf) for correct coding styles. A proper clocked process is written like this:process(clock,reset) begin if reset='1' -- initialization code elsif rising_edge(clock) -- or clock'event and clock='1' -- clocked statements end if; end process;This will ensure that Quartus recognises your code as a clocked process and will compile it properly.

which part of data in ethernet frame should be passed to CRC generator?

28 Replies

Altera_Forum
Honored Contributor
13 years ago
What CRC generator are you talking about? If you are using the TSE, it included its own CRC generator. Just send the Ethernet frame without the preample nor CRC.
Altera_Forum
Honored Contributor
13 years ago
TO_BE_DONE
Altera_Forum
Honored Contributor
13 years ago
TO_BE_DONE
Altera_Forum
Honored Contributor
13 years ago
First I'd appreciate if you could simplify your code and removed all the commented out code lines, it would make it easier to read.
Second you still aren't implementing your process right. I have no idea how Quartus will synthesize what you described, but it's probably not what you want. I suggest that you read this document (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf) for correct coding styles. A proper clocked process is written like this:
process(clock,reset) begin if reset='1' -- initialization code elsif rising_edge(clock) -- or clock'event and clock='1' -- clocked statements end if; end process;
This will ensure that Quartus recognises your code as a clocked process and will compile it properly.

Altera_Forum

Honored Contributor

13 years ago

i rewrite using rising_edge or falling_edge also not successful


LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity Transmit2 is
  port ( 
         CLOCK_50 : IN STD_LOGIC;
			SW : IN STD_LOGIC_VECTOR(17 DOWNTO 0)
       );
end entity Transmit2;
architecture syn of Transmit2 is
	component tether2 is
      port (  
            ff_tx_data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
	
				ff_tx_clk	: IN STD_LOGIC;
				ff_tx_eop	: IN STD_LOGIC;
				ff_tx_sop	: IN STD_LOGIC;
				ff_tx_wren 	: IN STD_LOGIC;
		
				read	: IN STD_LOGIC;
				writedata	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
				write	: IN STD_LOGIC;
				clk	: IN STD_LOGIC;
				reset	: IN STD_LOGIC;
				
				tx_clk	: IN STD_LOGIC;
				
				set_10	: IN STD_LOGIC;
				set_1000	: IN STD_LOGIC;
				ff_tx_crc_fwd	: IN STD_LOGIC;
				
				ff_tx_rdy	: OUT STD_LOGIC;
				
				readdata	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
				ena_10	: OUT STD_LOGIC;
				eth_mode	: OUT STD_LOGIC;
				ff_tx_a_full	: OUT STD_LOGIC;
				ff_tx_a_empty	: OUT STD_LOGIC;
				magic_wakeup	: OUT STD_LOGIC
           );
   end component tether2;
   --
   signal clk_10     : std_logic;
   signal clk_sys    : std_logic;
   signal pll_locked : std_logic;
   signal spi_cs_n   : std_logic;
	
	constant whilelooptrue :STD_LOGIC := '1';
	
	constant enableit : STD_LOGIC := '1';
	constant disableit : STD_LOGIC := '0';
	
	signal set_10_external : STD_LOGIC;
	signal set_100_external : STD_LOGIC;
	
	constant mac: std_logic_vector(47 downto 0) := X"CB90ADD27810";
	constant preamble : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"55"; -- 8 bits * 2 = 16, 4 bits one hex
	constant SFD : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"D5"; -- 8 bits * 2 = 16
	constant dest_mac_addr1 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"10";
	constant dest_mac_addr2 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"78";
	constant dest_mac_addr3 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"D2";
	constant dest_mac_addr4 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"AD";
	constant dest_mac_addr5 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"90";
	constant dest_mac_addr6 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"CB";
	
	constant src_mac_addr1 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"00";
	constant src_mac_addr2 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"12";
	constant src_mac_addr3 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"34";
	constant src_mac_addr4 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"56";
	constant src_mac_addr5 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"78";
	constant src_mac_addr6 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"90";
	constant payload : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"4B";
	constant wholepacketlength1 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"00";
	constant wholepacketlength2 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"20";
	
	constant emptyhex : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"00";
	constant emptytwobits : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
	
	signal tx_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
	signal macaddr_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
	signal CheckSumResult : STD_LOGIC_VECTOR (31 DOWNTO 0);
	signal CheckSumValid : STD_LOGIC;
	
	
	
	signal startpacket : STD_LOGIC;
	signal endpacket : STD_LOGIC;
	signal ff_tx_wren_enable : STD_LOGIC;
	signal ff_tx_rdy : STD_LOGIC;
	signal ena_10 : STD_LOGIC;
	signal eth_mode : STD_LOGIC;
	
	signal ff_tx_a_full : STD_LOGIC;
	signal ff_tx_a_empty	: STD_LOGIC;
	signal magic_wakeup : STD_LOGIC;
	signal beginwrite : STD_LOGIC;
begin
		H1:tether2 port map ( 
	
				ff_tx_data	=> tx_data,
				ff_tx_clk	=> CLOCK_50, 
				ff_tx_eop	=> endpacket, 
				ff_tx_sop	=> startpacket,
				ff_tx_wren 	=> ff_tx_wren_enable, 
				
				read	=> disableit,
				writedata	=> macaddr_data, 
				write	=> beginwrite, 
				clk	=> CLOCK_50, 
				reset	=> disableit, 
				
				tx_clk	=> CLOCK_50,
				
				set_10	=> set_10_external,
				set_1000	=> set_100_external, 
				ff_tx_crc_fwd	=> enableit, 
				
				ff_tx_rdy => ff_tx_rdy, 
				
				ena_10 => ena_10,
				eth_mode	=> eth_mode, --0 = 10/100Mbps, 1 = 1000Mbps : OUT STD_LOGIC;
				ff_tx_a_full	=> ff_tx_a_full,
				ff_tx_a_empty	=> ff_tx_a_empty, 
				magic_wakeup	=> magic_wakeup 
		);
	process(CLOCK_50)
	VARIABLE last_clk : std_logic := '0';
	VARIABLE counter : integer := 0;
	VARIABLE last_counter : integer := 0;
	begin
		if SW(0) = '1' then	
			if rising_edge(CLOCK_50) then
				
				if (counter = 0) then
					beginwrite <= '1';
					ff_tx_wren_enable <= enableit;
					
					macaddr_data <=mac(31 downto 0);
					
					startpacket <= enableit;
					tx_data <= dest_mac_addr1 & dest_mac_addr2 & dest_mac_addr3 & dest_mac_addr4;
				end if;
				if (counter = 1) then
					macaddr_data(15 downto 0) <=mac(47 downto 32);
					beginwrite <= '0';
					startpacket <= disableit;
					tx_data <= dest_mac_addr5 & dest_mac_addr6 & src_mac_addr1 & src_mac_addr2;
				end if;
				if (counter = 2) then
					tx_data <= src_mac_addr3 & src_mac_addr4 & src_mac_addr5 & src_mac_addr6;
				end if;
				if (counter = 3) then
					tx_data <= wholepacketlength1 & wholepacketlength2 & payload & emptyhex;
					endpacket <= enableit;
				end if;
				if (counter >= 4) then
					endpacket <= disableit;
					ff_tx_wren_enable <= disableit;
					beginwrite <= '0';
					counter := 0;
				end if;
				last_counter := counter;
				counter := counter + 1;
			end if;
		else
			beginwrite <= '0';
		end if;
		last_clk := CLOCK_50;
	end process;
 end architecture syn;

Altera_Forum

Honored Contributor

13 years ago


LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY tether2 IS
PORT ( ff_tx_data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		
		ff_tx_clk	: IN STD_LOGIC;
		ff_tx_eop	: IN STD_LOGIC;
		ff_tx_sop	: IN STD_LOGIC;
		ff_tx_wren	: IN STD_LOGIC;
		
		read	: IN STD_LOGIC;
		writedata	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		write	: IN STD_LOGIC;
		clk	: IN STD_LOGIC;
		reset	: IN STD_LOGIC;
		
		tx_clk	: IN STD_LOGIC;
		
		set_10	: IN STD_LOGIC;
		set_1000	: IN STD_LOGIC;
		ff_tx_crc_fwd	: IN STD_LOGIC;
		
		ff_tx_rdy	: OUT STD_LOGIC;
		
		readdata	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		
		ena_10	: OUT STD_LOGIC;
		eth_mode	: OUT STD_LOGIC;
		ff_tx_a_full	: OUT STD_LOGIC;
		ff_tx_a_empty	: OUT STD_LOGIC;
		magic_wakeup : OUT STD_LOGIC
		);
END tether2;
ARCHITECTURE Structural OF tether2 IS
	constant enableit : STD_LOGIC := '1';
	constant disableit : STD_LOGIC := '0';
	component tether
      PORT (
		ff_tx_data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		ff_tx_eop	: IN STD_LOGIC;
		ff_tx_err	: IN STD_LOGIC;
		ff_tx_mod	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		ff_tx_sop	: IN STD_LOGIC;
		ff_tx_wren	: IN STD_LOGIC;
		ff_tx_clk	: IN STD_LOGIC;
		ff_rx_rdy	: IN STD_LOGIC;
		ff_rx_clk	: IN STD_LOGIC;
		address	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		read	: IN STD_LOGIC;
		writedata	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		write	: IN STD_LOGIC;
		clk	: IN STD_LOGIC;
		reset	: IN STD_LOGIC;
		gm_rx_d	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		gm_rx_dv	: IN STD_LOGIC;
		gm_rx_err	: IN STD_LOGIC;
		m_rx_d	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		m_rx_en	: IN STD_LOGIC;
		m_rx_err	: IN STD_LOGIC;
		m_rx_col	: IN STD_LOGIC;
		m_rx_crs	: IN STD_LOGIC;
		tx_clk	: IN STD_LOGIC;
		rx_clk	: IN STD_LOGIC;
		set_10	: IN STD_LOGIC;
		set_1000	: IN STD_LOGIC;
		ff_tx_crc_fwd	: IN STD_LOGIC;
		xon_gen	: IN STD_LOGIC;
		xoff_gen	: IN STD_LOGIC;
		magic_sleep_n	: IN STD_LOGIC;
		ff_tx_rdy	: OUT STD_LOGIC;
		ff_rx_data	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		ff_rx_dval	: OUT STD_LOGIC;
		ff_rx_eop	: OUT STD_LOGIC;
		ff_rx_mod	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		ff_rx_sop	: OUT STD_LOGIC;
		rx_err	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
		readdata	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		waitrequest	: OUT STD_LOGIC;
		gm_tx_d	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		gm_tx_en	: OUT STD_LOGIC;
		gm_tx_err	: OUT STD_LOGIC;
		m_tx_d	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		m_tx_en	: OUT STD_LOGIC;
		m_tx_err	: OUT STD_LOGIC;
		ena_10	: OUT STD_LOGIC;
		eth_mode	: OUT STD_LOGIC;
		ff_tx_septy	: OUT STD_LOGIC;
		tx_ff_uflow	: OUT STD_LOGIC;
		ff_tx_a_full  : OUT STD_LOGIC;
		ff_tx_a_empty : OUT STD_LOGIC;
		rx_err_stat	: OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
		rx_frm_type	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		ff_rx_dsav	: OUT STD_LOGIC;
		ff_rx_a_full	: OUT STD_LOGIC;
		ff_rx_a_empty	: OUT STD_LOGIC;
		magic_wakeup	: OUT STD_LOGIC
	);
   end component tether;
	
	constant  ENABLE_MAGIC_DETECT: integer :=1;
	constant  ENABLE_MDIO: integer :=0;
	constant  ENABLE_SHIFT16: integer :=1;
	constant  ENABLE_SUP_ADDR: integer :=1;
	
	constant  CRC32GENDELAY: integer :=6;
	constant  MDIO_CLK_DIV: integer :=40;
	constant  ENA_HASH: integer :=1;
	constant  USE_SYNC_RESET: integer :=0;
	constant  STAT_CNT_ENA: integer :=1;
	constant  ENABLE_EXTENDED_STAT_REG: integer :=0;
	constant  ENABLE_HD_LOGIC: integer :=1;
	constant  REDUCED_INTERFACE_ENA: integer :=0;
	constant  CRC32S1L2_EXTERN: integer :=0;
	constant  ENABLE_GMII_LOOPBACK: integer :=1;
	constant  CRC32DWIDTH: integer :=8;
	constant  CUST_VERSION: integer :=0;
	constant  RESET_LEVEL: integer :=1;
	constant  CRC32CHECK16BIT: integer :=0;
	constant  ENABLE_MAC_FLOW_CTRL: integer :=1;
	constant  ENABLE_MAC_TXADDR_SET: integer :=1;
	constant  ENABLE_MAC_RX_VLAN: integer :=1;
	constant  ENABLE_MAC_TX_VLAN: integer :=1;
	constant  SYNCHRONIZER_DEPTH: integer :=4;
	constant  EG_FIFO: integer :=2048;
	constant  EG_ADDR: integer :=11;
	constant  ING_FIFO: integer :=2048;
	constant  ENABLE_ENA: integer :=32;
	constant ING_ADDR : integer  := 11;
	constant  RAM_TYPE: string :="AUTO";
	constant  INSERT_TA: integer :=0;
	constant  ENABLE_MACLITE: integer :=0;
	constant  MACLITE_GIGE: integer :=0;
	constant  MAX_CHANNELS: integer :=0;
	--
	signal gm_tx_d2	:STD_LOGIC_VECTOR (7 DOWNTO 0) := "00000000";
	signal gm_tx_en2	: STD_LOGIC := '0';
	signal gm_tx_err2 : STD_LOGIC := '0';
	signal m_tx_d2 : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
	signal m_tx_en2 : STD_LOGIC := '0';
	signal m_tx_err2	: STD_LOGIC := '0';
	--
	signal ff_rx_data : STD_LOGIC_VECTOR (31 DOWNTO 0) := x"00000000";
	
	constant mac_addr : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"10";--"1078D2AD90CB"; -- address of register stored mac address
	signal ff_tx_mod : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; 
	
	signal rx_err_stat	: STD_LOGIC_VECTOR (17 DOWNTO 0) := "000000000000000000";
	signal rx_frm_type	: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
	
	signal ff_rx_dval2 : STD_LOGIC;
	signal readdata2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
	signal waitrequest2 : STD_LOGIC;
	signal ff_rx_eop : STD_LOGIC;
	signal rx_err : STD_LOGIC_VECTOR (5 DOWNTO 0);
	signal ff_rx_sop : STD_LOGIC;
	signal m_tx_en : STD_LOGIC;
	signal ff_tx_septy	: STD_LOGIC;
	signal tx_ff_uflow	: STD_LOGIC;
	signal ff_rx_dsav : STD_LOGIC;
	signal ff_rx_a_full : STD_LOGIC;
	signal ff_rx_a_empty : STD_LOGIC;
	signal magic_wakeup2 : STD_LOGIC;
BEGIN
H2:tether port map (
			
		ff_tx_data	=> ff_tx_data, 
		ff_tx_eop	=> ff_tx_eop, 
		ff_tx_err	=> disableit, 
		ff_tx_mod	=> ff_tx_mod, 
		ff_tx_sop	=> ff_tx_sop, 
		ff_tx_wren	=> ff_tx_wren, 
		ff_tx_clk	=> ff_tx_clk, 
		ff_rx_rdy	=> enableit, 
		ff_rx_clk	=> ff_tx_clk, 
		address	=> mac_addr,
		read	=> read, 
		writedata => writedata, 
		write	=> write, 
		clk	=> clk, 
		reset	=> disableit, 
		gm_rx_d	=> "00000000",
		gm_rx_dv	=> disableit,
		gm_rx_err => disableit, 
		m_rx_d	=> "0000", 
		m_rx_en	=> disableit, 
		m_rx_err	=> disableit, 
		m_rx_col	=> disableit, 
		m_rx_crs	=> disableit, 
		tx_clk	=> tx_clk, 
		rx_clk	=> tx_clk, 
		set_10	=> set_10, 
		set_1000	=> set_1000, 
		ff_tx_crc_fwd	=> disableit,
		xon_gen	=> disableit,
		xoff_gen	=> disableit,
		magic_sleep_n	=> disableit, 
		ff_tx_rdy	=> ff_tx_rdy,
		ff_rx_data	=> ff_rx_data, 
		ff_rx_dval	=> ff_rx_dval2,
		ff_rx_eop	=> ff_rx_eop, 
		ff_rx_mod	=> ff_tx_mod, 
		ff_rx_sop	=> ff_rx_sop,
		rx_err	=> rx_err,
		readdata	=> readdata2,
		waitrequest	=> waitrequest2,
		gm_tx_d	=> gm_tx_d2, 
		gm_tx_en	=> gm_tx_en2, 
		gm_tx_err => gm_tx_err2, 
		m_tx_d	=> m_tx_d2,
		m_tx_en	=> m_tx_en, 
		m_tx_err	=> m_tx_err2, 
		ena_10	=> ena_10,
		eth_mode	=> eth_mode,
		ff_tx_septy	=> ff_tx_septy,
		tx_ff_uflow	=> tx_ff_uflow,
		ff_tx_a_full	=> ff_tx_a_full,
		ff_tx_a_empty	=> ff_tx_a_empty,
		rx_err_stat	=> rx_err_stat,
		rx_frm_type	=> rx_frm_type,
		ff_rx_dsav	=> ff_rx_dsav,
		ff_rx_a_full	=> ff_rx_a_full,
		ff_rx_a_empty	=> ff_rx_a_empty,
		magic_wakeup	=> magic_wakeup
		);
		
END Structural;

Altera_Forum
Honored Contributor
13 years ago
I would put the if rising_edge(CLOCK_50) before the if SW(0) = '1', but maybe this still synthesizes right.
You could use Signaltap on the Avalon Stream interface to check that you are sending the correct stream to the MAC.
There are still a few problems I think:[list][*]You aren't checking the the 'ready' signal on the ff_tx interface. A data word on the avalon stream interface will only be transmitted if both 'valid' and 'ready' are asserted at the same time. Therefore you should only increase the counter when you know the MAC read your data word.
[*]check that the "Align packet headers to 32-bit boundary" option isn't checked on the TSE parameters ("MAC Options") tab. If this option is enabled then you need to send 16 '0' bits before you start the packet.
[*]You are not initializing the MAC before you are using it. You should at least set TX_ENA to 1 before sending anything. It is described on page 6-6 of the datasheet. Generally you can have a look at the Altera TSE driver to see how the TSE can be initialized.
[*]You are generating a packet that is less than 64 bytes, and I'm not sure the TSE will automatically add the padding bytes for you[/list]
Altera_Forum
Honored Contributor
13 years ago
it's my first time to use signaltap, could you teach me how to use it in this situation

setup i add SW[0] , right hand side i choose clock as CLOCK_50, trigger use pre-trigger and condition 1 and sequantial
trigger in i use rising_edge and SW[0]

then i try to press read data , said trigger condition not met in SW[0] in central part
then i press analysis, it do not have response , i got a question when doing it in signaltap, there is no output parameter in top layer, how can signaltap see the data, if i need to add back eth0 as output parameter in top layer, how to connect them with this Triple speed IP when data is just 4 bits
Altera_Forum
Honored Contributor
13 years ago
Do you get any data out when you aren't using a trigger? Are you sure that SW[0] actually changes?
As for your other question, you can probe any signal with SignalTap, including the internal ones. By default you only see the toplevel signals, but in the node finder you can go deeper in the hierarchy.
Altera_Forum
Honored Contributor
13 years ago
One thing i still do not understand is that without connect the pin defined in pin assignment csv with the triple speed IP, how can it be output to ethernet?
and how to connect data[4] with data[32]

Forum Discussion

which part of data in ethernet frame should be passed to CRC generator?

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