which part of data in ethernet frame should be passed to CRC generator?

i rewrite using rising_edge or falling_edge also not successful

LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity Transmit2 is
  port ( 
         CLOCK_50 : IN STD_LOGIC;
			SW : IN STD_LOGIC_VECTOR(17 DOWNTO 0)
       );
end entity Transmit2;
architecture syn of Transmit2 is
	component tether2 is
      port (  
            ff_tx_data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
	
				ff_tx_clk	: IN STD_LOGIC;
				ff_tx_eop	: IN STD_LOGIC;
				ff_tx_sop	: IN STD_LOGIC;
				ff_tx_wren 	: IN STD_LOGIC;
		
				read	: IN STD_LOGIC;
				writedata	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
				write	: IN STD_LOGIC;
				clk	: IN STD_LOGIC;
				reset	: IN STD_LOGIC;
				
				tx_clk	: IN STD_LOGIC;
				
				set_10	: IN STD_LOGIC;
				set_1000	: IN STD_LOGIC;
				ff_tx_crc_fwd	: IN STD_LOGIC;
				
				ff_tx_rdy	: OUT STD_LOGIC;
				
				readdata	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
				ena_10	: OUT STD_LOGIC;
				eth_mode	: OUT STD_LOGIC;
				ff_tx_a_full	: OUT STD_LOGIC;
				ff_tx_a_empty	: OUT STD_LOGIC;
				magic_wakeup	: OUT STD_LOGIC
           );
   end component tether2;
   --
   signal clk_10     : std_logic;
   signal clk_sys    : std_logic;
   signal pll_locked : std_logic;
   signal spi_cs_n   : std_logic;
	
	constant whilelooptrue :STD_LOGIC := '1';
	
	constant enableit : STD_LOGIC := '1';
	constant disableit : STD_LOGIC := '0';
	
	signal set_10_external : STD_LOGIC;
	signal set_100_external : STD_LOGIC;
	
	constant mac: std_logic_vector(47 downto 0) := X"CB90ADD27810";
	constant preamble : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"55"; -- 8 bits * 2 = 16, 4 bits one hex
	constant SFD : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"D5"; -- 8 bits * 2 = 16
	constant dest_mac_addr1 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"10";
	constant dest_mac_addr2 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"78";
	constant dest_mac_addr3 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"D2";
	constant dest_mac_addr4 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"AD";
	constant dest_mac_addr5 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"90";
	constant dest_mac_addr6 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"CB";
	
	constant src_mac_addr1 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"00";
	constant src_mac_addr2 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"12";
	constant src_mac_addr3 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"34";
	constant src_mac_addr4 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"56";
	constant src_mac_addr5 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"78";
	constant src_mac_addr6 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"90";
	constant payload : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"4B";
	constant wholepacketlength1 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"00";
	constant wholepacketlength2 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"20";
	
	constant emptyhex : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"00";
	constant emptytwobits : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
	
	signal tx_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
	signal macaddr_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
	signal CheckSumResult : STD_LOGIC_VECTOR (31 DOWNTO 0);
	signal CheckSumValid : STD_LOGIC;
	
	
	
	signal startpacket : STD_LOGIC;
	signal endpacket : STD_LOGIC;
	signal ff_tx_wren_enable : STD_LOGIC;
	signal ff_tx_rdy : STD_LOGIC;
	signal ena_10 : STD_LOGIC;
	signal eth_mode : STD_LOGIC;
	
	signal ff_tx_a_full : STD_LOGIC;
	signal ff_tx_a_empty	: STD_LOGIC;
	signal magic_wakeup : STD_LOGIC;
	signal beginwrite : STD_LOGIC;
begin
		H1:tether2 port map ( 
	
				ff_tx_data	=> tx_data,
				ff_tx_clk	=> CLOCK_50, 
				ff_tx_eop	=> endpacket, 
				ff_tx_sop	=> startpacket,
				ff_tx_wren 	=> ff_tx_wren_enable, 
				
				read	=> disableit,
				writedata	=> macaddr_data, 
				write	=> beginwrite, 
				clk	=> CLOCK_50, 
				reset	=> disableit, 
				
				tx_clk	=> CLOCK_50,
				
				set_10	=> set_10_external,
				set_1000	=> set_100_external, 
				ff_tx_crc_fwd	=> enableit, 
				
				ff_tx_rdy => ff_tx_rdy, 
				
				ena_10 => ena_10,
				eth_mode	=> eth_mode, --0 = 10/100Mbps, 1 = 1000Mbps : OUT STD_LOGIC;
				ff_tx_a_full	=> ff_tx_a_full,
				ff_tx_a_empty	=> ff_tx_a_empty, 
				magic_wakeup	=> magic_wakeup 
		);
	process(CLOCK_50)
	VARIABLE last_clk : std_logic := '0';
	VARIABLE counter : integer := 0;
	VARIABLE last_counter : integer := 0;
	begin
		if SW(0) = '1' then	
			if rising_edge(CLOCK_50) then
				
				if (counter = 0) then
					beginwrite <= '1';
					ff_tx_wren_enable <= enableit;
					
					macaddr_data <=mac(31 downto 0);
					
					startpacket <= enableit;
					tx_data <= dest_mac_addr1 & dest_mac_addr2 & dest_mac_addr3 & dest_mac_addr4;
				end if;
				if (counter = 1) then
					macaddr_data(15 downto 0) <=mac(47 downto 32);
					beginwrite <= '0';
					startpacket <= disableit;
					tx_data <= dest_mac_addr5 & dest_mac_addr6 & src_mac_addr1 & src_mac_addr2;
				end if;
				if (counter = 2) then
					tx_data <= src_mac_addr3 & src_mac_addr4 & src_mac_addr5 & src_mac_addr6;
				end if;
				if (counter = 3) then
					tx_data <= wholepacketlength1 & wholepacketlength2 & payload & emptyhex;
					endpacket <= enableit;
				end if;
				if (counter >= 4) then
					endpacket <= disableit;
					ff_tx_wren_enable <= disableit;
					beginwrite <= '0';
					counter := 0;
				end if;
				last_counter := counter;
				counter := counter + 1;
			end if;
		else
			beginwrite <= '0';
		end if;
		last_clk := CLOCK_50;
	end process;
 end architecture syn;