which part of data in ethernet frame should be passed to CRC generator?

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY tether2 IS
PORT ( ff_tx_data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		
		ff_tx_clk	: IN STD_LOGIC;
		ff_tx_eop	: IN STD_LOGIC;
		ff_tx_sop	: IN STD_LOGIC;
		ff_tx_wren	: IN STD_LOGIC;
		
		read	: IN STD_LOGIC;
		writedata	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		write	: IN STD_LOGIC;
		clk	: IN STD_LOGIC;
		reset	: IN STD_LOGIC;
		
		tx_clk	: IN STD_LOGIC;
		
		set_10	: IN STD_LOGIC;
		set_1000	: IN STD_LOGIC;
		ff_tx_crc_fwd	: IN STD_LOGIC;
		
		ff_tx_rdy	: OUT STD_LOGIC;
		
		readdata	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		
		ena_10	: OUT STD_LOGIC;
		eth_mode	: OUT STD_LOGIC;
		ff_tx_a_full	: OUT STD_LOGIC;
		ff_tx_a_empty	: OUT STD_LOGIC;
		magic_wakeup : OUT STD_LOGIC
		);
END tether2;
ARCHITECTURE Structural OF tether2 IS
	constant enableit : STD_LOGIC := '1';
	constant disableit : STD_LOGIC := '0';
	component tether
      PORT (
		ff_tx_data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		ff_tx_eop	: IN STD_LOGIC;
		ff_tx_err	: IN STD_LOGIC;
		ff_tx_mod	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		ff_tx_sop	: IN STD_LOGIC;
		ff_tx_wren	: IN STD_LOGIC;
		ff_tx_clk	: IN STD_LOGIC;
		ff_rx_rdy	: IN STD_LOGIC;
		ff_rx_clk	: IN STD_LOGIC;
		address	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		read	: IN STD_LOGIC;
		writedata	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		write	: IN STD_LOGIC;
		clk	: IN STD_LOGIC;
		reset	: IN STD_LOGIC;
		gm_rx_d	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		gm_rx_dv	: IN STD_LOGIC;
		gm_rx_err	: IN STD_LOGIC;
		m_rx_d	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		m_rx_en	: IN STD_LOGIC;
		m_rx_err	: IN STD_LOGIC;
		m_rx_col	: IN STD_LOGIC;
		m_rx_crs	: IN STD_LOGIC;
		tx_clk	: IN STD_LOGIC;
		rx_clk	: IN STD_LOGIC;
		set_10	: IN STD_LOGIC;
		set_1000	: IN STD_LOGIC;
		ff_tx_crc_fwd	: IN STD_LOGIC;
		xon_gen	: IN STD_LOGIC;
		xoff_gen	: IN STD_LOGIC;
		magic_sleep_n	: IN STD_LOGIC;
		ff_tx_rdy	: OUT STD_LOGIC;
		ff_rx_data	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		ff_rx_dval	: OUT STD_LOGIC;
		ff_rx_eop	: OUT STD_LOGIC;
		ff_rx_mod	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		ff_rx_sop	: OUT STD_LOGIC;
		rx_err	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
		readdata	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		waitrequest	: OUT STD_LOGIC;
		gm_tx_d	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		gm_tx_en	: OUT STD_LOGIC;
		gm_tx_err	: OUT STD_LOGIC;
		m_tx_d	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		m_tx_en	: OUT STD_LOGIC;
		m_tx_err	: OUT STD_LOGIC;
		ena_10	: OUT STD_LOGIC;
		eth_mode	: OUT STD_LOGIC;
		ff_tx_septy	: OUT STD_LOGIC;
		tx_ff_uflow	: OUT STD_LOGIC;
		ff_tx_a_full  : OUT STD_LOGIC;
		ff_tx_a_empty : OUT STD_LOGIC;
		rx_err_stat	: OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
		rx_frm_type	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		ff_rx_dsav	: OUT STD_LOGIC;
		ff_rx_a_full	: OUT STD_LOGIC;
		ff_rx_a_empty	: OUT STD_LOGIC;
		magic_wakeup	: OUT STD_LOGIC
	);
   end component tether;
	
	constant  ENABLE_MAGIC_DETECT: integer :=1;
	constant  ENABLE_MDIO: integer :=0;
	constant  ENABLE_SHIFT16: integer :=1;
	constant  ENABLE_SUP_ADDR: integer :=1;
	
	constant  CRC32GENDELAY: integer :=6;
	constant  MDIO_CLK_DIV: integer :=40;
	constant  ENA_HASH: integer :=1;
	constant  USE_SYNC_RESET: integer :=0;
	constant  STAT_CNT_ENA: integer :=1;
	constant  ENABLE_EXTENDED_STAT_REG: integer :=0;
	constant  ENABLE_HD_LOGIC: integer :=1;
	constant  REDUCED_INTERFACE_ENA: integer :=0;
	constant  CRC32S1L2_EXTERN: integer :=0;
	constant  ENABLE_GMII_LOOPBACK: integer :=1;
	constant  CRC32DWIDTH: integer :=8;
	constant  CUST_VERSION: integer :=0;
	constant  RESET_LEVEL: integer :=1;
	constant  CRC32CHECK16BIT: integer :=0;
	constant  ENABLE_MAC_FLOW_CTRL: integer :=1;
	constant  ENABLE_MAC_TXADDR_SET: integer :=1;
	constant  ENABLE_MAC_RX_VLAN: integer :=1;
	constant  ENABLE_MAC_TX_VLAN: integer :=1;
	constant  SYNCHRONIZER_DEPTH: integer :=4;
	constant  EG_FIFO: integer :=2048;
	constant  EG_ADDR: integer :=11;
	constant  ING_FIFO: integer :=2048;
	constant  ENABLE_ENA: integer :=32;
	constant ING_ADDR : integer  := 11;
	constant  RAM_TYPE: string :="AUTO";
	constant  INSERT_TA: integer :=0;
	constant  ENABLE_MACLITE: integer :=0;
	constant  MACLITE_GIGE: integer :=0;
	constant  MAX_CHANNELS: integer :=0;
	--
	signal gm_tx_d2	:STD_LOGIC_VECTOR (7 DOWNTO 0) := "00000000";
	signal gm_tx_en2	: STD_LOGIC := '0';
	signal gm_tx_err2 : STD_LOGIC := '0';
	signal m_tx_d2 : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
	signal m_tx_en2 : STD_LOGIC := '0';
	signal m_tx_err2	: STD_LOGIC := '0';
	--
	signal ff_rx_data : STD_LOGIC_VECTOR (31 DOWNTO 0) := x"00000000";
	
	constant mac_addr : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"10";--"1078D2AD90CB"; -- address of register stored mac address
	signal ff_tx_mod : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; 
	
	signal rx_err_stat	: STD_LOGIC_VECTOR (17 DOWNTO 0) := "000000000000000000";
	signal rx_frm_type	: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
	
	signal ff_rx_dval2 : STD_LOGIC;
	signal readdata2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
	signal waitrequest2 : STD_LOGIC;
	signal ff_rx_eop : STD_LOGIC;
	signal rx_err : STD_LOGIC_VECTOR (5 DOWNTO 0);
	signal ff_rx_sop : STD_LOGIC;
	signal m_tx_en : STD_LOGIC;
	signal ff_tx_septy	: STD_LOGIC;
	signal tx_ff_uflow	: STD_LOGIC;
	signal ff_rx_dsav : STD_LOGIC;
	signal ff_rx_a_full : STD_LOGIC;
	signal ff_rx_a_empty : STD_LOGIC;
	signal magic_wakeup2 : STD_LOGIC;
BEGIN
H2:tether port map (
			
		ff_tx_data	=> ff_tx_data, 
		ff_tx_eop	=> ff_tx_eop, 
		ff_tx_err	=> disableit, 
		ff_tx_mod	=> ff_tx_mod, 
		ff_tx_sop	=> ff_tx_sop, 
		ff_tx_wren	=> ff_tx_wren, 
		ff_tx_clk	=> ff_tx_clk, 
		ff_rx_rdy	=> enableit, 
		ff_rx_clk	=> ff_tx_clk, 
		address	=> mac_addr,
		read	=> read, 
		writedata => writedata, 
		write	=> write, 
		clk	=> clk, 
		reset	=> disableit, 
		gm_rx_d	=> "00000000",
		gm_rx_dv	=> disableit,
		gm_rx_err => disableit, 
		m_rx_d	=> "0000", 
		m_rx_en	=> disableit, 
		m_rx_err	=> disableit, 
		m_rx_col	=> disableit, 
		m_rx_crs	=> disableit, 
		tx_clk	=> tx_clk, 
		rx_clk	=> tx_clk, 
		set_10	=> set_10, 
		set_1000	=> set_1000, 
		ff_tx_crc_fwd	=> disableit,
		xon_gen	=> disableit,
		xoff_gen	=> disableit,
		magic_sleep_n	=> disableit, 
		ff_tx_rdy	=> ff_tx_rdy,
		ff_rx_data	=> ff_rx_data, 
		ff_rx_dval	=> ff_rx_dval2,
		ff_rx_eop	=> ff_rx_eop, 
		ff_rx_mod	=> ff_tx_mod, 
		ff_rx_sop	=> ff_rx_sop,
		rx_err	=> rx_err,
		readdata	=> readdata2,
		waitrequest	=> waitrequest2,
		gm_tx_d	=> gm_tx_d2, 
		gm_tx_en	=> gm_tx_en2, 
		gm_tx_err => gm_tx_err2, 
		m_tx_d	=> m_tx_d2,
		m_tx_en	=> m_tx_en, 
		m_tx_err	=> m_tx_err2, 
		ena_10	=> ena_10,
		eth_mode	=> eth_mode,
		ff_tx_septy	=> ff_tx_septy,
		tx_ff_uflow	=> tx_ff_uflow,
		ff_tx_a_full	=> ff_tx_a_full,
		ff_tx_a_empty	=> ff_tx_a_empty,
		rx_err_stat	=> rx_err_stat,
		rx_frm_type	=> rx_frm_type,
		ff_rx_dsav	=> ff_rx_dsav,
		ff_rx_a_full	=> ff_rx_a_full,
		ff_rx_a_empty	=> ff_rx_a_empty,
		magic_wakeup	=> magic_wakeup
		);
		
END Structural;