which part of data in ethernet frame should be passed to CRC generator?

First I'd appreciate if you could simplify your code and removed all the commented out code lines, it would make it easier to read.

Second you still aren't implementing your process right. I have no idea how Quartus will synthesize what you described, but it's probably not what you want. I suggest that you read this document (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf) for correct coding styles. A proper clocked process is written like this:

process(clock,reset)
begin
  if reset='1'
    
    -- initialization code
  elsif rising_edge(clock)  -- or clock'event and clock='1'
    
    -- clocked statements
  end if;
end process;

This will ensure that Quartus recognises your code as a clocked process and will compile it properly.