which part of data in ethernet frame should be passed to CRC generator?

it's my first time to use signaltap, could you teach me how to use it in this situation

setup i add SW[0] , right hand side i choose clock as CLOCK_50, trigger use pre-trigger and condition 1 and sequantial

trigger in i use rising_edge and SW[0]

then i try to press read data , said trigger condition not met in SW[0] in central part

then i press analysis, it do not have response , i got a question when doing it in signaltap, there is no output parameter in top layer, how can signaltap see the data, if i need to add back eth0 as output parameter in top layer, how to connect them with this Triple speed IP when data is just 4 bits