Honored ContributorIn Verilog or system verilog, If using async reset the process sensitivity list must be written as below:
1, always_ff @ (posedge clk, negedge rst_async_n) 2, always_ff @ (posedge clk, posedge rst_async_n) My question is what's the differ of above 2 expressions?
Honored ContributorPls compare below 4 codes:
1, module reset_gen ( output rst_sync_n, input clk, rst_async_n); logic rst_s1, rst_s2; always_ff @ (posedge clk, posedge rst_async_n) if (rst_async_n) begin rst_s1 <= 1'b0; rst_s2 <= 1'b0; end else begin rst_s1 <= 1'b1; rst_s2 <= rst_s1; end assign rst_sync_n = rst_s2; endmodule 2, module[/B] reset_gen ( output rst_sync_n, input clk, rst_async_n); logic rst_s1, rst_s2; always_ff @ (posedge clk, posedge rst_async_n) if (rst_async_n) begin rst_s1 <= 1'b1; rst_s2 <= 1'b1; end else begin rst_s1 <= 1'b0; rst_s2 <= rst_s1; end assign rst_sync_n = rst_s2; endmodule 3, logic rst_s1, rst_s2;[/B] always_ff @ (posedge clk, negedge rst_async_n)if (!rst_async_n) begin
rst_s1 <= 1'b0;
rst_s2 <= 1'b0;
end
else begin
rst_s1 <= 1'b1;
rst_s2 <= rst_s1;
end
assign rst_sync_n = rst_s2; 4, logic rst_s1, rst_s2; always_ff @ (posedge clk, negedge rst_async_n)
if (!rst_async_n) begin
rst_s1 <= 1'b1;
rst_s2 <= 1'b1;
end
else begin
rst_s1 <= 1'b0;
rst_s2 <= rst_s1;
end
assign rst_sync_n = rst_s2;
[/B][/B]
Honored ContributorBTW, I'm Verilog fresh man!
Honored Contributorposedge means the transition from 0 to 1
negedge the oposit transition from 1 to 0 usualy a clock is used as posedge, so everytime your clock signals goes from 0 to 1 using posedge or negedge for the reset condition depends on the logic level you use or your design if you reset signal is negativ logic meaning a 0 is reset and 1 is normal running mode, then you want to reset your logic as soon as the reset condition is valid. that is true as soon as your negativ reset leaves the 1 condition. so you use negedge reset (1->0) also it is important to notice that any signal beside your clock in the always content is treated asyncronously. if you would write always @ ( posedge clk ) if ( reset ) // reset else // normal mode then your reset is a syncrounous reset and the reset condition is checked with the next clock cycle if you write always @ ( posedge clk or posedge reset ) if ( reset ) // reset else // normal mode then your reset is executed as soon as this condition occurs regardless how your clock signal is. this is a asyncroun resetHonored ContributorHonored ContributorIt's clear, thanks a lot!
