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Altera_Forum
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16 years ago

What's the differ of the posedge and negedge?

In Verilog or system verilog, If using async reset the process sensitivity list must be written as below: 1, always_ff @ (posedge clk, negedge rst_async_n) 2, always_ff @ (posedge clk, pos...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Pls compare below 4 codes:

1,

module reset_gen (

output rst_sync_n,

input clk, rst_async_n);

logic rst_s1, rst_s2;

always_ff @ (posedge clk, posedge rst_async_n)

if (rst_async_n) begin

rst_s1 <= 1'b0;

rst_s2 <= 1'b0;

end

else begin

rst_s1 <= 1'b1;

rst_s2 <= rst_s1;

end

assign rst_sync_n = rst_s2;

endmodule

2,

module[/B] reset_gen (

output rst_sync_n,

input clk, rst_async_n);

logic rst_s1, rst_s2;

always_ff @ (posedge clk, posedge rst_async_n)

if (rst_async_n) begin

rst_s1 <= 1'b1;

rst_s2 <= 1'b1;

end

else begin

rst_s1 <= 1'b0;

rst_s2 <= rst_s1;

end

assign rst_sync_n = rst_s2;

endmodule

3,

logic rst_s1, rst_s2;[/B]

always_ff @ (posedge clk, negedge rst_async_n)

if (!rst_async_n) begin

rst_s1 <= 1'b0;

rst_s2 <= 1'b0;

end

else begin

rst_s1 <= 1'b1;

rst_s2 <= rst_s1;

end

assign rst_sync_n = rst_s2;

4,

logic rst_s1, rst_s2;

always_ff @ (posedge clk, negedge rst_async_n)

if (!rst_async_n) begin

rst_s1 <= 1'b1;

rst_s2 <= 1'b1;

end

else begin

rst_s1 <= 1'b0;

rst_s2 <= rst_s1;

end

assign rst_sync_n = rst_s2;

[/B][/B]