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Altera_Forum
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16 years ago

What's the differ of the posedge and negedge?

In Verilog or system verilog, If using async reset the process sensitivity list must be written as below: 1, always_ff @ (posedge clk, negedge rst_async_n) 2, always_ff @ (posedge clk, pos...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

--- Quote Start ---

1, always_ff @ (posedge clk, negedge rst_async_n)

2, always_ff @ (posedge clk, posedge rst_async_n)

--- Quote End ---

1 - Async reset is active low.

2 - Async reset is active high.

In other words, opposite polarity of the asynchronous reset signal.