What should we expect to obtain from synthesis?

Hello,

I understand from Verilog specification, that variables only appearing in the event expression (without a posedge or negedge keyword) are ignored.

If you intend an asynchronous "logic loop" latch, you should write as such.

if (a | b | c | d)

out=1'b1;

Or

out = out | a | b | c | d;

The problem is, that a logic loop, unlike a flipflop has no default power-on state, so out could be high from the beginning. Cause a reset condition would be necessary in real live anyway, this is more a theoretical issue.

out = (out & ~reset) | a | b | c | d;

Regards,

Frank

Thanks for your reply.

My purpose was to use "always @" to detect any input change, rather than the combinational logic, so that avoid to figure out the implementation details. Do you mean two points?

1, out is ignored because it only appears in event expression(I didn't know this constraint);

2, out hasn't default power on state.

Yes. Furthermore you should consider that @(a,b,c,d) event expression can't create somewhat like an edge detector. You can use posedge or negedge with a clock variable and create a synchronuous flipflop. But level change event expression doesn't have an equivalent logic circuit that would actually detect an input change as you intended. You may regard the construct as non-synthesizable so far.

I suggest to code the logic function that is actually intended, I have written my understanding of the function in a synthesizable way.

Thank you. Finally I wrote as below:

module edge_detection(a,b,c,clr,out);

input a,b,c,clr;

output out;

wire pos_clock,neg_clock;

assign pos_clock=a^b^c;

assign neg_clock=!(a^b^c);

reg out0, out1;

DFFT DFF0(1,out0,pos_clock,clr);

DFFT DFF1(1,out1,neg_clock,clr);

assign out=out0|out1;

endmodule

module DFFT(q,d,clock,reset);

input q,clock,reset;

output reg d;

always @(posedge clock or posedge reset)

if(reset) d<=0'b0;

else d<=q;

endmodule

But I am curious about the constraint you mentioned, that ignoring of "out". I can't find it in the IEEE Std 1364-2001 file. Can you give me an instruction about where or which page I can get it? I want to know more about it.

Hello,

to start with a simple thing. What I had remembered from Verilog specification is actually under 9.7.5 implicit event expression list and doesn't apply here. So probably the original construct could be valid Verilog code in behavioral simulation, but to my opinion can't be synthesizable.

The flipflop bidirectional edge detection in contrast is basically synthesizable and the code, after a few corrections, understandable to Quartus (I also changed DFF d and q to their usual meaning), as the RTL viewer shows.

module edge_detection(a,b,c,clr,out);
input a,b,c,clr;
output out;
wire pos_clock,neg_clock;
assign pos_clock=a^b^c;
assign neg_clock=!(a^b^c);
wire out0,ou1;
wire eins = 1'b1;
DFFT DFF0(eins,out0,pos_clock,clr);
DFFT DFF1(eins,out1,neg_clock,clr);
assign out=out0|out1;
assign out1a=out1;
endmodule
module DFFT(d,q,clock,reset);
input d,clock,reset;
output reg q;
always @(posedge clock or posedge reset)
if(reset) q<=1'b0;
else q<=d;
endmodule

I would expect logic of this kind primarly in 60th/70th TTL or 80th PLD designs, it also could be appropriate for a glitch trigger catching events otherwise unseen by a sampling clock, but it would be less suitable for today's common synchronous CPLD and FPGA designs. The construct is working well as such, but the problems arise when connectimg clr and out to another clock domain. In normal cases, when a, b, c is not expected to have glitches shorter than a main clock period, one would use synchronous edge detection instead. That's e. g. how Quartus SignalTap operates a bidirectional edge trigger.

Regards,

Frank