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Altera_Forum
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18 years ago

What should we expect to obtain from synthesis?

Hello, this topic is a Verilog beginner's cranky confusion. I want to do a detector, which senses the status transition for several inputs. As an instance, an MCU system needs an interrupt to k...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Yes. Furthermore you should consider that @(a,b,c,d) event expression can't create somewhat like an edge detector. You can use posedge or negedge with a clock variable and create a synchronuous flipflop. But level change event expression doesn't have an equivalent logic circuit that would actually detect an input change as you intended. You may regard the construct as non-synthesizable so far.

I suggest to code the logic function that is actually intended, I have written my understanding of the function in a synthesizable way.