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Altera_Forum's avatar
Altera_Forum
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18 years ago

What should we expect to obtain from synthesis?

Hello, this topic is a Verilog beginner's cranky confusion. I want to do a detector, which senses the status transition for several inputs. As an instance, an MCU system needs an interrupt to k...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Thanks for your reply.

My purpose was to use "always @" to detect any input change, rather than the combinational logic, so that avoid to figure out the implementation details. Do you mean two points?

1, out is ignored because it only appears in event expression(I didn't know this constraint);

2, out hasn't default power on state.