What should we expect to obtain from synthesis?

Thank you. Finally I wrote as below:

module edge_detection(a,b,c,clr,out);

input a,b,c,clr;

output out;

wire pos_clock,neg_clock;

assign pos_clock=a^b^c;

assign neg_clock=!(a^b^c);

reg out0, out1;

DFFT DFF0(1,out0,pos_clock,clr);

DFFT DFF1(1,out1,neg_clock,clr);

assign out=out0|out1;

endmodule

module DFFT(q,d,clock,reset);

input q,clock,reset;

output reg d;

always @(posedge clock or posedge reset)

if(reset) d<=0'b0;

else d<=q;

endmodule

But I am curious about the constraint you mentioned, that ignoring of "out". I can't find it in the IEEE Std 1364-2001 file. Can you give me an instruction about where or which page I can get it? I want to know more about it.