What should we expect to obtain from synthesis?

Hello,

I understand from Verilog specification, that variables only appearing in the event expression (without a posedge or negedge keyword) are ignored.

If you intend an asynchronous "logic loop" latch, you should write as such.

if (a | b | c | d)

out=1'b1;

Or

out = out | a | b | c | d;

The problem is, that a logic loop, unlike a flipflop has no default power-on state, so out could be high from the beginning. Cause a reset condition would be necessary in real live anyway, this is more a theoretical issue.

out = (out & ~reset) | a | b | c | d;

Regards,

Frank