What should we expect to obtain from synthesis?

Hello,

to start with a simple thing. What I had remembered from Verilog specification is actually under 9.7.5 implicit event expression list and doesn't apply here. So probably the original construct could be valid Verilog code in behavioral simulation, but to my opinion can't be synthesizable.

The flipflop bidirectional edge detection in contrast is basically synthesizable and the code, after a few corrections, understandable to Quartus (I also changed DFF d and q to their usual meaning), as the RTL viewer shows.

module edge_detection(a,b,c,clr,out);
input a,b,c,clr;
output out;
wire pos_clock,neg_clock;
assign pos_clock=a^b^c;
assign neg_clock=!(a^b^c);
wire out0,ou1;
wire eins = 1'b1;
DFFT DFF0(eins,out0,pos_clock,clr);
DFFT DFF1(eins,out1,neg_clock,clr);
assign out=out0|out1;
assign out1a=out1;
endmodule
module DFFT(d,q,clock,reset);
input d,clock,reset;
output reg q;
always @(posedge clock or posedge reset)
if(reset) q<=1'b0;
else q<=d;
endmodule

I would expect logic of this kind primarly in 60th/70th TTL or 80th PLD designs, it also could be appropriate for a glitch trigger catching events otherwise unseen by a sampling clock, but it would be less suitable for today's common synchronous CPLD and FPGA designs. The construct is working well as such, but the problems arise when connectimg clr and out to another clock domain. In normal cases, when a, b, c is not expected to have glitches shorter than a main clock period, one would use synchronous edge detection instead. That's e. g. how Quartus SignalTap operates a bidirectional edge trigger.

Regards,

Frank