What is mean of Zero IC delays?

IC delay means Interconnect delays i.e. the delay an interconnect takes to connect between two logic elements (i hope you now get it).

Now if you tick zero IC delays time quest will only show you the path having logic elements and your timing analysis is basically done only on cell delays so its normal that the setup timings wont be violated (In some cases hold timing gets violated though).

This is basically done post map but i recommend that after post fit do not enable the option as the real path of the design will be IC delay + Cell delay on which i think your timings should be closed.

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IC delay means Interconnect delays i.e. the delay an interconnect takes to connect between two logic elements (i hope you now get it).

Now if you tick zero IC delays time quest will only show you the path having logic elements and your timing analysis is basically done only on cell delays so its normal that the setup timings wont be violated (In some cases hold timing gets violated though).

This is basically done post map but i recommend that after post fit do not enable the option as the real path of the design will be IC delay + Cell delay on which i think your timings should be closed.

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Thanks very much. I am sorry I am a little confused by your last sentence. But my understanding is, I should disable this option if I do is post fit in Create Timing Netlist, right?

Thanks

The idea of 0 IC delay timing model is to exclude interconnect delays from timing model.

If your design does not pass it then it will not pass when you turn the interconnect delay on.

If it passes then hope is in the way that it may pass with interconnect delay added.

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The idea of 0 IC delay timing model is to exclude interconnect delays from timing model.

If your design does not pass it then it will not pass when you turn the interconnect delay on.

If it passes then hope is in the way that it may pass with interconnect delay added.

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Hi Kaz, do you mean: If I enable Zero IC delay in post fit mode and the design has some failed paths, then it is impossible to get the design pass timing (make the timing closure)?

But I actually confront: my design has no violated paths in post fit mode with Zero IC delay disable. But when I enable it, there appears some failed paths whose hold time is violated.

And timing closure means meet time requirments, right? I am not 100% sure what is mean of "timing closure".

Thanks

If your design passes timing with cell delay plus IC delay then you passed.

Then you don't really need to worry about the case when 0 IC delay is applied because it is unrealistic and is meant as early diagnostic measure.

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If your design passes timing with cell delay plus IC delay then you passed.

Then you don't really need to worry about the case when 0 IC delay is applied because it is unrealistic and is meant as early diagnostic measure.

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Timing closure is the name of what "TimeQuest and fitter and optionally synthesis stage" have to do to achieve best results for timing which may be pass or fail.

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Thanks very much, Kaz

Plus to add to what you mentioned about failing of hold paths, i did mentioned that with 0 IC delays you might fail hold timings because generally Quartus adds some intentional delays during place and route in the form of interconnect delays to meet hold timings which was not available during 0 IC delay netlist.

If you are meeting timings Post-fit with disabling 0 IC delays then you have met timings and no need to worry about your issue :)

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Plus to add to what you mentioned about failing of hold paths, i did mentioned that with 0 IC delays you might fail hold timings because generally Quartus adds some intentional delays during place and route in the form of interconnect delays to meet hold timings which was not available during 0 IC delay netlist.

If you are meeting timings Post-fit with disabling 0 IC delays then you have met timings and no need to worry about your issue :)

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Thanks very much!