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Altera_Forum
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13 years ago

What is mean of Zero IC delays?

I found there is an option "Zero IC delays" in Create Timing Netlist. I try to figure out what it is, but it seems I can't find too much useful information in ALtera website. What is that? And ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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If your design passes timing with cell delay plus IC delay then you passed.

Then you don't really need to worry about the case when 0 IC delay is applied because it is unrealistic and is meant as early diagnostic measure.

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Timing closure is the name of what "TimeQuest and fitter and optionally synthesis stage" have to do to achieve best results for timing which may be pass or fail.

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Thanks very much, Kaz