What is mean of Zero IC delays?

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IC delay means Interconnect delays i.e. the delay an interconnect takes to connect between two logic elements (i hope you now get it).

Now if you tick zero IC delays time quest will only show you the path having logic elements and your timing analysis is basically done only on cell delays so its normal that the setup timings wont be violated (In some cases hold timing gets violated though).

This is basically done post map but i recommend that after post fit do not enable the option as the real path of the design will be IC delay + Cell delay on which i think your timings should be closed.

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Thanks very much. I am sorry I am a little confused by your last sentence. But my understanding is, I should disable this option if I do is post fit in Create Timing Netlist, right?

Thanks