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The idea of 0 IC delay timing model is to exclude interconnect delays from timing model.
If your design does not pass it then it will not pass when you turn the interconnect delay on.
If it passes then hope is in the way that it may pass with interconnect delay added.
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Hi Kaz, do you mean: If I enable Zero IC delay in post fit mode and the design has some failed paths, then it is impossible to get the design pass timing (make the timing closure)?
But I actually confront: my design has no violated paths in post fit mode with Zero IC delay disable. But when I enable it, there appears some failed paths whose hold time is violated.
And timing closure means meet time requirments, right? I am not 100% sure what is mean of "timing closure".
Thanks
Honored Contributor
