Forum Discussion
Altera_Forum
Honored Contributor
13 years agoPlus to add to what you mentioned about failing of hold paths, i did mentioned that with 0 IC delays you might fail hold timings because generally Quartus adds some intentional delays during place and route in the form of interconnect delays to meet hold timings which was not available during 0 IC delay netlist.
If you are meeting timings Post-fit with disabling 0 IC delays then you have met timings and no need to worry about your issue :)